Abstract: The invention includes a method for manufacturing a merged contact in a window, comprising opening a window to one of a source and a drain of a field effect transistor and to and only partially overlapping a gate electrode of the field effect transistor, and depositing an electrical conductor connecting the gate electrode with one of the source and the drain to provide a merged contact between the gate and one of the source and the drain. Also described are devices made thereby.
Abstract: A micromechanical component, particularly a pressure sensor, includes a substrate, made of semiconductor material; a functional layer provided epitactically on substrate; a hollow space being provided between substrate and functional layer defining a diaphragm region of functional layer; and below diaphragm region, on substrate, one or more spacers being provided, for preventing adhesion of diaphragm region to substrate during deformation. Also described is an appropriate manufacturing method.
Type:
Grant
Filed:
May 16, 2001
Date of Patent:
May 28, 2002
Assignee:
Robert Bosch GmbH
Inventors:
Hubert Benzel, Frank Schaefer, Heinz-Georg Vossenberg
Abstract: A process for forming a polycrystalline TFT LCD is provided, thereby greatly reducing the manufacturing cost and time. The process includes steps of performing a first masking procedure to define a gate conductive region, successively forming an insulation layer, an amorphous channel semiconductor layer, a catalytic layer and a doped semiconductor layer, performing a second masking procedure to remove portions of the semiconductor layer and the catalytic layer to define an electrode region, performing a thermal treatment to respectively convert the electrode region and the amorphous semiconductor channel layer into a source/drain region and a crystalline semiconductor channel layer by the catalytic layer, performing a third masking procedure to define data lines, performing a fourth masking procedure to form a contact hole, and performing a fifth masking procedure to define a transparent pixel electrode region, thereby forming the TFT.
Abstract: A method for making frontside contact to a substrate through an SOI structure thereon is provided. An etching step is undertaken to form a trench in the SOI structure so as to expose and define a rough surface of the substrate. Then, a thin insulating layer, for example SiO2, is formed over the exposed surface of the substrate, this insulating layer being irregular because of its formation over the relatively rough etched surface. Contact material is provided in the trench, and electrical potential is applied across the contact and substrate sufficient to increase the conductivity of the insulating layer, i.e., to break down the insulating layer. Nitrogen may be implanted into the exposed surface of the substrate to slow subsequent growth of the insulating layer, resulting in an even thinner insulating layer, i.e., one even less resistant to breakdown upon application of electrical potential thereacross.
Abstract: An insulated lattice is prepared with a plurality of lattice oriented atoms to create a substantially planar surface having a lattice arrangement. Any unsatisfied chemical bonds are terminated along the substantially planar surface by placing atoms at the site of the unsatisfied chemical bonds to terminate the unsatisfied chemical bonds and insulate the surface to form a platform. In one aspect of the invention, the insulator atoms are removed at predetermined locations. Atoms to form the atomic chain are placed at predetermined locations on the insulated lattice platform to form a first atomic chain which behaves as one of a conductor, a semiconductor and an insulator. A second atomic chain is also placed at predetermined locations on the insulated lattice platform so that the second chain behaves as another of a conductor, a semiconductor and an insulator.
Type:
Grant
Filed:
February 10, 1999
Date of Patent:
December 18, 2001
Assignees:
Board of Regents of the Leland Stanford Junior
University, Research Development Corp
Abstract: A method for forming a GaN-based semiconductor layer includes the steps of: forming a ZnO buffer layer on one of a glass substrate and a silicon substrate; and epitaxially growing a GaN-based semiconductor layer on the ZnO buffer layer by using an electron cyclotron resonance--molecular beam epitaxy (ECR-MBE) method.