Abstract: An enhanced DRAM contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data. This data corresponds to data stored in the DRAM at a particular address. When an address is supplied to the DRAM, it is compared to the address of the data stored in the cache. If the addresses are the same, then the cache data is read at SRAM speeds. The DRAM is decoupled from this read. The DRAM also remains idle during this cache read unless the system opts to precharge or refresh the DRAM. Refresh or precharge occur concurrently with the cache read. If the addresses are not the same, then the DRAM is accessed and the embedded register is reloaded with the data at that new DRAM address.

Abstract: A method and apparatus is disclosed for reliably storing data to be written to a peripheral device subsystem. The method disclosed includes the following steps. A first peripheral device controller, which includes a cache memory, receives write data from a central processor, stores it in its cache memory, and transmits a copy of it to a second peripheral device controller via a communications path. The second controller, which also includes a cache memory, stores the copy of the write data transmitted to it in its cache memory. Meanwhile the first controller processes the write data. In the event the first controller fails, the second controller processes the write data stored in its cache memory. The apparatus disclosed includes a central processor which generates write data. A first peripheral device controller, which includes a cache memory, is coupled to the central processor.

Abstract: Herein disclosed is an information processing apparatus having a synchronous storage and the synchronous storage which can resume an operation continuing from before an interruption without hindrance even after a series of read/write operations have been interrupted and a read/write of internal condition values has been performed in a scanning operation or the like. The information processing apparatus successively selects information stored in address backup registers in two stages and data backup registers in two stages and outputs the selected information to the synchronous storage when a normal operation is resumed, thereby restoring an address data register, a data input register and a data output register to the same conditions as before the interruption of the normal operation. This invention is applicable to a synchronous storage accessible in synchronism with a system clock and an information processing apparatus having such synchronous storage.

Abstract: A control logic unit outputs a group of encoded control signals that have less redundancy than the FPU signals needed to control a floating point processor, thus requiring fewer signal lines using less area. Decoders electrically connected between the control logic unit and the floating point processor decode the control signals to provide the FPU signals. If the number of control signals is one less than the number of FPU signals, a priority encoder is used as the decoder, unless the FPU signals include a power savings signal. Otherwise a custom decoder is used. The most active signal of the group of FPU signals is selected as the signal to be eliminated when a priority encoder is used.

Abstract: A filtered command port architecture for a memory array is disclosed. A command controller is directly connected to the memory array and receives command instructions from an external microprocessor via an address and data bus. A command clock is used to latch commands from the data bus into a command decoder. A timing signal is used to filter incoming signals from the data bus which are asserted for less than a predetermined amount of time. A state decoder then tracks a sequence of commands from the command decoder and performs an appropriate action in response to the commands.

Abstract: A disk array data storage system has a plurality of storage disks and a disk array controller for coordinating transfer of user data to and from the storage disks. A memory manager is provided to manage memory allocation and data storage on the disk array. The memory manager maintains a sufficient quantity of hot spare storage space that can be made available for reconstructing the user data and restoring redundancy in the event one of the storage disks fails. Until a disk fails, however, the memory manager uses the hot spare space to store user and redundant data while guaranteeing that the storage space can be used for rebuilding following a storage disk failure. In this manner, all storage disks in the array are used to store user data, and additionally to maintain storage space that can be easily made available for purposes of hot spare in the event of disk failure.

Abstract: A register address space is defined with a capacity large enough to accommodate substantial growth in the number of required registers. Unused register locations are reserved for future use. Access requests directed to reserved addresses are redirected to a physical register containing the same stored value that would be returned if a physical register were associated with the reserved address to which the access was originally directed. The physical register is separate from any central processing unit.

Abstract: Within a data processing system implementing L1 and L2 caches and stream filters and buffers, prefetching of cache lines is performed in a progressive manner. In one mode, data may not be prefetched. In a second mode, two cache lines are prefetched wherein one line is prefetched into the L1 cache and the next line is prefetched into a stream buffer. In a third mode, more than two cache lines are prefetched at a time. As a result, additional cache lines are progressively prefetched to a data cache as the sequentiality of the accessing of cache lines in memory is demonstrated through sequential addressing requests along a data stream. Furthermore, the stream is physically distributed. In other words, at least one line, but not all lines, of the stream are placed within the cache.

Abstract: A single dirty bit is maintained in a memory controller for each cache line of a cached memory system using a cache write-back policy. The dirty bit is set after each write access, is reset after each read access in which a cache miss occurs, and is left unchanged after all other memory accesses. The dirty bit is used to select a delay value for submitting a retry request packet after a cache miss occurred in a memory access. The delay value minimizes memory access time by allowing for a write-back operation only when necessary.

Abstract: In case that software is written on a recording medium at physical addresses thereof in units of a prescribed size and the software is subsequently executed upon being read out of the recording medium from the physical addresses in the order of logical addresses, the corresponding relationship between the logical addresses of the software and the physical addresses conforming to the logical addresses, as well as a checking program for preventing unlawful use of the software, is added on to the main body of the software, which is then recorded on an original. Before execution of the software that has been recorded on a recording medium (the original or a copy), the corresponding relationship between the logical and physical addresses on this recording medium is obtained by the checking program. The corresponding relationship obtained and the corresponding relationship that has been added to the software are compared.

Abstract: A method and apparatus for an improving memory access bandwidth that can be used in a digital signal processor (DSP) (500) is accomplished by modifying addresses (302, 304) generated by an address generation unit (AGU) (102) of the DSP (500). Two addresses (302, 304) are generated by the AGU (102). One of the two addresses (302) is used to address two parallel memory blocks (308, 310) in a single memory simultaneously, and the other address (304) is modified by a modulo increment function to produce two additional addresses (404, 406) that also address the parallel memory blocks (308, 310). With such a method and apparatus, four simultaneous memory reads can occur, effectively doubling the memory access bandwidth in the DSP system (500) without modification of the AGU (102) or program controller (510).

Abstract: A hierarchic disk array data storage system has multiple storage disks that define a physical storage space and a RAID management system that maps the physical storage space into two virtual storage spaces. The RAID-level virtual storage space presents the physical storage space as mirror and parity RAID areas where the mirror RAID areas contain mirror allocation blocks to store data according to RAID Level 1 and the parity RAID areas contain parity allocation blocks to store data according to RAID Level 5. The application-level virtual storage space presents the physical storage space as multiple virtual blocks. The RAID management system migrates data between the mirror and parity RAID areas to optimize performance and reliability. To ensure that sufficient space is retained for this migration, the RAID management system limits the number of virtual blocks that are allocated in the mirror RAID areas.

Abstract: A data driven type information processor includes a firing control unit, an operation unit, and a program storage unit. Each of these units has a function of initializing itself in response to an initialization data packet in a specific form.

Abstract: A hierarchic disk array data storage system has a disk array with multiple storage disks and a disk array controller which coordinates data transfer to and from the disks. The storage disks define a physical storage space. A RAID management system maps a RAID-level virtual storage space onto the physical storage space. The RAID-level virtual storage space presents the physical storage space as multiple RAID areas. The RAID areas include mirror RAID areas which contain mirror allocation blocks to store data according to mirror redundancy and parity RAID areas which contain parity allocation blocks to store data according to parity redundancy. The RAID management system dynamically migrates data between the mirror and parity RAID areas in a manner which optimizes performance and data reliability. As new storage requests are made, the RAID management system evaluates the existing storage conditions and computes a total virtual capacity that is available to the user given a disk array configuration.

Abstract: A set associative cache system in a computer system having a lower memory is provided with a plurality of cache memory sets. A cache data memory contains a plurality of cache lines to store data in units of blocks corresponding to data stored in the lower memory. A cache tag memory stores lower memory addresses for data stored in the cache lines. The plurality of cache memory sets have different numbers of cache lines. A read/write section reads out data stored in the lower memory into the plurality of cache lines and writing data in the plurality of cache lines back to the lower memory.

Abstract: A small computer system interface (SCSI) controller for continuously or intermittently performing communication of plural sets of data. The SCSI controller includes a data register for temporarily storing a set of data, a SCSI interface for transmitting the data stored in the data register in units of 2 bytes and for receiving data from another SCSI controller in units of 2 bytes, a byte counter for counting the number of bytes of data that is transmitted from or received by the SCSI interface, an internal processor for controlling initial setting of a target count value of the byte counter, and a transfer control circuit for controlling transmission of the data stored in the data register from the SCSI interface and reception of data by the data register via the SCSI interface. In data communication in units of 2 bytes, the SCSI controller can prevent transfer of dummy data that is ineffective, to thereby provide efficient data communication.

Abstract: A first determination unit determines whether or not the number of storage racks which stores each of a plurality of disks into which informations stored in one copying source disk are copied exceeds the number of the plurality of disks. A copying unit copies the informations stored in the copying source disk into each of the disks in order and determines whether or not a copying process is normal, when it is determined that the number of the storage racks exceeds the number of the plurality of disks. A storage control unit controls the disks so as to store the disks from one edge side of the storage rack in order when the copying process is normal, and controls the disks so as to store the disks from other edge side of the storage racks in order when the copying process is not normal. In another embodiment, duplication ceases when the number of copied disks totals one less than the number of storage racks.

Abstract: A memory controller in a computer system is described. The memory controller maintains a directory comprising a plurality of entries. Each entry is associated with a memory block. The memory controller maintains an entry of the directory in a modified fine bit vector format when a memory block associated with the entry is cached in one or more nodes all of which are within a single partition of the computer system. The entry when maintained in the modified fine bit vector format comprises a partition field storing information identifying the single partition, and a modified fine bit vector field storing information identifying nodes in the single partition where the memory block is cached. The memory controller maintains the entry in a modified coarse bit vector format when the memory block is cached in multiple nodes distributed among P partitions of the computer system, where P is greater than one.

Abstract: There is provided a Direct Access Memory Unit (DAu) that is associated with a remote processor module in a multi-processing system. The DAU performs Direct Memory Access (DMA) operations independently of a Central Processing Unit (CPU) in the remote processor module. The CPU requests a DMA by writing information relevant to the DMA to the remote processor's memory. The address of each control block is written to a circular queue, also in the remote processor's memory. The DAU determines if there are any control blocks to process and if so, the DAU will perform the DMA operation (reading data from or writing data to the memory of the host processor), all without the intervention of the CPU of the remote processor module. The CPU adds a new control block by loading its address in a location in the circular queue that is ahead of the circular queue location that the DAU is processing. The CPU can abort a pending DMA request during DAU operations by setting a skip bit in the control block.

Abstract: A micro-computer system using a DRAM can refresh the DRAM in a certain interval cycle to maintain the memory contents or refresh the DRAM memory even when the system is set into the standby mode and the clock generator has stopped providing clock timing signals to the memory refreshing circuit. Accordingly, the DRAM memory is refreshed by automatically changing from the interval refresh mode to the self refresh mode when the system operation changes from the normal operation to the standby operation, thus achieving low system power consumption.