Abstract: A field-effect transistor and a method for manufacturing a field-effect transistor is disclosed. One embodiment includes a substrate having a surface along which a trench is implemented, wherein the trench has a trench bottom and a trench edge. A source area is implemented at the trench edge and a gate electrode at least partially implemented in the trench and separated from the substrate by an insulation layer. The field-effect transistor includes a drain electrode at a side of the substrate facing away from the surface. An additional electrode is implemented between the gate electrode and the trench bottom and electrically insulated from the substrate and an electrical connection between the additional electrode and the gate electrode, wherein the electrical connection has a predetermined ohmic resistance value.

Abstract: A memory cell of a nonvolatile semiconductor memory device according to an embodiment of the invention has a MONOS structure. The charge storage layer of the memory cell includes insulating material layers. The relationship between the conduction band edge energy and valance band edge energy of the insulating material layers either increases gradually or decreases gradually from the tunnel insulating film toward the block insulating film. Furthermore, when the relative permittivity of the block insulating film is expresses as ?r, an energy barrier between the charge storage layer and the block insulating film is equal to or larger than 4.5 ?r?2/3 (eV) and is equal to or smaller than 3.8 (eV).

Abstract: A system and method is provided for transmitting a signal to a plurality of slave devices (e.g., memory devices, etc.) via a communication circuit having a plurality of segments that are substantially equal in length and/or impedance. Specifically, according to one embodiment of the invention, an electronic system includes a processor, a plurality of memory devices, and a communication circuit (i.e., a bus) having a central node and a plurality of segments. Specifically, the plurality of segments are used to connect the plurality of devices (e.g., the processor, the plurality of memory devices) to the central node. For example, the processor is connected to the central node via a primary segment, the first memory device (M0) is connected to the central node via a first segment, etc. In one embodiment of the invention, the plurality of segments are substantially equal in length. In other words, the central node is substantially electrically-equidistant from each memory device.

Abstract: A crack stopping structure is disclosed. The crack stopping structure includes a semiconductor substrate having a die region, a die seal ring region, and a scribe line region; a metal interconnect structure disposed on the semiconductor substrate of the scribe line region; and a plurality of dielectric layers disposed on the semiconductor substrate of the die region, the die seal ring region, and the scribe line region. The dielectric layers include a first opening exposing the surface of the metal interconnect structure of the scribe line region and a second opening exposing the dielectric layer adjacent to the metal interconnect structure such that the metal interconnect structure and the exposed portion of the dielectric layer form a step.

Abstract: In a semiconductor memory device which includes a shared sense amplifier portion, a pair of memory cell portions disposed on opposite sides of the shared sense amplifier portion, a pair of transfer gates between the pair of memory cell portions and the shared sense amplifier portion, and bit lines constituting a plurality of bit line pairs and connecting the pair of memory cell portions to each other through the pair of transfer gates and the shared sense amplifier portion, the bit lines in a bit line pair of the plurality of bit line pairs are twisted at a substantial center between the pair of transfer gates on the opposite sides.

Abstract: A phase change memory device and a method of forming the same are provided. The phase change memory device includes a conducting electrode in a dielectric layer, a bottom electrode over the conducting electrode, a phase change layer over the bottom electrode, and a top electrode over the phase change layer. The phase change memory device may further include a heat sink layer between the phase change layer and the top electrode. The resistivities of the bottom electrode and the top electrode are preferably greater than the resistivity of the phase change material in the crystalline state.

Abstract: A method for fabricating a semiconductor device includes forming an insulating pattern over a semiconductor substrate. An epitaxial growth layer is formed over the semiconductor substrate exposed by the insulating pattern to fill the insulating pattern with the epitaxial growth layer. A recess gate having a recess channel is formed. The recess channel is disposed between two neighboring insulating patterns.

Abstract: A miniaturized sensor such as a micro-accelerometer includes a sensor chip having a sensor element mounted thereon, with the sensor element being oriented with its central axes passing through the corners of the sensor chip. The corners of the sensor element are thereby located substantially apart from the corners of the sensor chip, so that bending deformation which displaces corners of the sensor chip is substantially prevented from causing displacement of corners of the sensor element. Detection inaccuracy resulting from such displacement can thereby be prevented or reduced.

Abstract: Example embodiments relate to an organic semiconductor polymer, in which fused thiophenes having liquid crystal properties and aromatic compounds having N-type semiconductor properties are alternately included in the main chain of the polymer, an organic active layer, an organic thin film transistor (OTFT), and an electronic device including the same, and methods of preparing the organic semiconductor polymer, and fabricating the organic active layer, the OTFT and the electronic device using the same. This organic semiconductor polymer has improved organic solvent solubility, processability, and thin film properties, and may impart increased charge mobility and decreased off-state leakage current when applied to the channel layer of the organic thin film transistor.

Abstract: The invention relates to a metallization for an IGBT or a diode. In the case of this metallization, a copper layer (10, 12) having a layer thickness of approximately 50 ?m is applied to the front side and/or rear side of a semiconductor body (1) directly or if need be via a diffusion barrier layer (13, 14). The layer (8, 12) has a specific heat capacity that is at least a factor of 2 higher than the specific heat capacity of the semiconductor body (1). It simultaneously serves for producing a field stop layer (5) by proton implantation through the layer (12) from the rear side and for masking a proton or helium implantation for the purpose of charge carrier lifetime reduction from the front side of the chip (1).

Abstract: A composition comprising a plurality of molecules. Each of the molecules has a core comprising at least one aromatic ring and at least three pendant arms chemically bonded to the core. The pendant arms comprise a phenylene-terminated thiophene oligomer.

Abstract: Disclosed is a semiconductor storage device having a trench around a bit-line diffusion region in an area of a p-well, which constitutes a memory cell area, that is not covered by a word line and a select gate that intersects the word line. An insulating film is buried in the trench.

Abstract: A thin film capacitor with a trench structure having a base substance and a pair of electrodes provided on the base substance, and a dielectrode provided between the electrodes. The trench pattern is configured to have a first pattern and a second pattern separate from the first pattern. The first pattern having a plurality of protrusions provided upright at predetermined intervals, and the second pattern separate from the first pattern having a plurality of recesses provided at predetermined intervals, are provided at the side of the base substance where the dielectric film is formed. Trenches are each defined by the outer wall of each protrusion and the inner wall of each recess.

Abstract: After a fabrication process intended to miniaturize semiconductor devices, a surface area of a stack capacitor in a random access memory (RAM) is significantly reduced and capacity thereof is thus decreased, which in turn causes the capacitor not able to function properly. The present invention provides a composite lower electrode structure consisting of an exterior annular pipe and a central pillar having concave-convex surfaces to increase a surface area of the capacitor within a limited memory cell so as to enhance the capacity. To reinforce intensity of a structure of the capacitor, the exterior annular pipe has an elliptic radial cross section and a thicker thickness along a short axis direction.

Abstract: An electronic device comprising a polymer of Formula or Structure (I) wherein R1 is hydrogen, halogen, a suitable hydrocarbon, or a heteroatom containing group; R2 is hydrogen, a suitable hydrocarbon, a heteroatom containing group, or a halogen; R3 and R4 are independently a suitable hydrocarbon, hydrogen, a heteroatom containing group, or a halogen; Ar is an aromatic component; x, y, a, b, and c represent the number of groups or rings, respectively; Z represents sulfur, oxygen, selenium, or NR wherein R is hydrogen, alkyl, or aryl; and n represents the number of repeating units.

Abstract: A semiconductor device of the present invention comprises a logic circuit to which a power supply voltage, a sub-power supply voltage, a ground voltage and a sub-ground voltage are supplied; a driver for generating the sub-power supply voltage and the sub-ground voltage based on the power supply voltage and the ground voltage; a first wiring layer including a sub-power supply line for supplying the sub-power supply voltage and a sub-ground line for supplying the sub-ground voltage; a second wiring layer including source/drain lines for MOS transistors; a third wiring layer including a main power supply line for supplying the power supply voltage and a main ground line for supplying the ground voltage and arranged opposite to the first wiring layer to sandwich the second wiring layer; via structures for connecting the source/drain lines of the second wiring layer to the other layers.

Abstract: Improved thin film transistor array panels are provided. In one embodiment, a panel includes a plurality of gate lines, data lines, and a plurality of switching elements connected to the gate lines and the data lines. An interlayer insulating layer is formed between the gate lines and the data lines. A passivation layer covering the gate lines, the data lines, and the switching elements is also provided having a plurality of first contact holes exposing portions of the data lines, wherein the switching elements and the pixel electrodes are connected through the first contact holes. A plurality of contact assistants are formed on the passivation layer and are connected to the data lines through a plurality of second contact holes in the passivation layer. A plurality of auxiliary lines are connected to the data lines through a plurality of third contact holes in the interlayer insulating layer.

Abstract: Embodiments discussed herein relate to processes of producing a field stop zone within a semiconductor substrate by implanting dopant atoms into the substrate to form a field stop zone between a channel region and a surface of the substrate, at least some of the dopant atoms having energy levels of at least 0.15 eV below the energy level of the conduction band edge of semiconductor substrate; and laser annealing the field stop zone.

Abstract: This invention pertains to a composition for a dielectric thin film, which is capable of being subjected to a low-temperature process. Specifically, the invention is directed to a metal oxide dielectric thin film formed using the composition, a preparation method thereof, a transistor device comprising the dielectric thin film, and an electronic device comprising the transistor device. The electronic device to which the dielectric thin film has been applied exhibits excellent electrical properties, thereby satisfying both a low operating voltage and a high charge mobility.

Abstract: Provided are a semiconductor light emitting device and a method of fabricating the same. The semiconductor light emitting device comprises: a light emitting structure comprising a first conductive type semiconductor layer, an active layer under the first conductive type semiconductor layer, and a second conductive type semiconductor layer under the active layer; a reflective electrode layer under the light emitting structure, and an outer protection layer at an outer circumference of the reflective electrode layer.