Patents Examined by Kendrick Lam
  • Patent number: 10990317
    Abstract: Memory devices and systems with automatic background precondition upon powerup, and associated methods, are disclosed herein. In one embodiment, a memory device includes a memory array having a plurality of memory cells at intersections of memory rows and memory columns. The memory device further includes sense amplifiers corresponding to the memory rows. When the memory device powers on, the memory device writes one or more memory cells of the plurality of memory cells to a random data state before executing an access command received from a user, a memory controller, or a host device of the memory device. In some embodiments, to write the one or more memory cells, the memory device fires multiple memory rows at the same time without powering corresponding sense amplifiers such that data stored on memory cells of the multiple memory rows is overwritten and corrupted.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: April 27, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Anthony D. Veches, Debra M. Bell, James S. Rehmeyer, Robert Bunnell, Nathaniel J. Meier
  • Patent number: 10956086
    Abstract: A memory controller circuit is disclosed which is coupleable to a first memory circuit, such as DRAM, and includes: a first memory control circuit to read from or write to the first memory circuit; a second memory circuit, such as SRAM; a second memory control circuit adapted to read from the second memory circuit in response to a read request when the requested data is stored in the second memory circuit, and otherwise to transfer the read request to the first memory control circuit; predetermined atomic operations circuitry; and programmable atomic operations circuitry adapted to perform at least one programmable atomic operation. The second memory control circuit also transfers a received programmable atomic operation request to the programmable atomic operations circuitry and sets a hazard bit for a cache line of the second memory circuit.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: March 23, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Tony M. Brewer
  • Patent number: 10942663
    Abstract: Techniques are provided for inlining data in inodes of a file system. In an example, data (e.g., a file) is to be written to storage. Where the data is small enough to fit in an inode, it can be written to a dynamic area of the inode. Where dynamic attributes of the inode conflict with storing the data, the dynamic attributes can be spilled to a metadata block. Where the inlined data becomes too large to be stored in the inode, it can be spilled to a data block, and a metadata tree can be written to the inode. Where data that was previously too large to inline is truncated so that now it can be written to the inode, the data is inlined in the inode from a data block.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: March 9, 2021
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Attilio Rao, Dmitri Chmelev
  • Patent number: 10915445
    Abstract: A method, computer readable medium, and system are disclosed for a distributed cache that provides multiple processing units with fast access to a portion of data, which is stored in local memory. The distributed cache is composed of multiple smaller caches, and each of the smaller caches is associated with at least one processing unit. In addition to a shared crossbar network through which data is transferred between processing units and the smaller caches, a dedicated connection is provided between two or more smaller caches that form a partner cache set. Transferring data through the dedicated connections reduces congestion on the shared crossbar network. Reducing congestion on the shared crossbar network increases the available bandwidth and allows the number of processing units to increase. A coherence protocol is defined for accessing data stored in the distributed cache and for transferring data between the smaller caches of a partner cache set.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: February 9, 2021
    Assignee: NVIDIA Corporation
    Inventors: Wishwesh Anil Gandhi, Tanmoy Mandal, Ravi Kiran Manyam, Supriya Shrihari Rao
  • Patent number: 10860478
    Abstract: A method and an apparatus for storing data are provided. The method includes: acquiring target data, the target data including first key-value pair data, object data or array data, the key-value pair data including key data and value data, the object data including second key-value pair data, and the array data including object data; determining an object data number of the object data included in the target data, an array data number of the array data included in the target data, a first key-value pair data number of the first key-value pair data included in the target data, and a second key-value pair data number of the second key-value pair data included in the target data; determining a storage space based on the determined numbers; and storing the target data into the storage space.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: December 8, 2020
    Assignee: BEIJING BAIDU NETCOM SCIENCE AND TECHNOLOGY CO., LTD.
    Inventors: Yang Wang, Xunchao Song, Pengcheng Yuan, Xiaobo Liu, Xi Chen
  • Patent number: 10678470
    Abstract: Securing redundancy for physical storage devices that are extended in units smaller than physical storage devices configuring one RAID group. When d+r pieces of physical storage devices are connected by connecting r pieces of physical storage devices, a computer: adds v×r pieces of logical chunks; adds n×v pieces of physical storage areas in each additional storage device; changes mapping information to associate n pieces of physical storage areas with v×(d+r) pieces of logical chunks under a mapping condition; in response to a write request of user data, creates redundant data; determines a first logical chunk corresponding to the write request; and respectively writes n pieces of element data including the user data and the redundant data into n pieces of physical storage areas corresponding to the first logical chunk, based on the mapping information.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: June 9, 2020
    Assignee: Hitachi, Ltd.
    Inventors: Takeru Chiba, Shintaro Ito, Mitsuo Hayasaka
  • Patent number: 10629269
    Abstract: A read table management method for a solid state storage device includes the following steps. If the lowest computation value in a hot group is lower than the highest computation value in a cold group when a read table adjusting process is enabled, a first read voltage set corresponding to the lowest computation value in the hot group and a second read voltage set corresponding to the highest computation value in the cold group are swapped with each other. Consequently, the second read voltage set becomes to belong to the hot group, and the first read voltage set becomes to belong to the cold group.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: April 21, 2020
    Assignee: SOLID STATE STORAGE TECHNOLOGY CORPORATION
    Inventors: Shih-Jia Zeng, Chun-Wei Kuo, Kuan-Chun Chen, Jen-Chien Fu