Abstract: A computer chip includes a plurality of modules interconnected in an on-chip data transfer network configured in a mesh of rings, ring or rings, or polygonal hub topology. The data transfer network includes links or buses and a switchpoint. The links or buses are configured in a ring topology as a ring of rings or polygonal hub with each group of links or bus including a portion which is shared with a portion of another group of links bus. The bus switchpoint is positioned as a hub at the intersection of the ring of rings. The switchpoint is operable to route data from a source to a destination so that the modules are operable to communicate with each other through the links or buses, and the switchpoint. In various embodiments, the modules are coupled to the links or buses and/or the switchpoint.