Patents Examined by Kenneth E. Horton
  • Patent number: 5324494
    Abstract: A method is described for producing silicon carbide particles using a silicon source material and a hydrocarbon. The method is efficient and is characterized by high yield. Finely divided silicon source material is contacted with hydrocarbon at a temperature of 400.degree. C. to 1000.degree. C. where the hydrocarbon pyrolyzes and coats the particles with carbon. The particles are then heated to 1100.degree. C. to 1600.degree. C. to cause a reaction between the ingredients to form silicon carbide of very small particle size. No grinding of silicon carbide is required to obtain small particles. The method may be carried out as a batch process or as a continuous process.
    Type: Grant
    Filed: January 21, 1993
    Date of Patent: June 28, 1994
    Assignee: Midwest Research Institute
    Inventor: Gregory C. Glatzmaier
  • Patent number: 5302555
    Abstract: A method for anisotropically depositing a dielectric from a precursor gas in a reactor is disclosed. The method includes reduced pressure, reduced oxygen/precursor gas flow ratio, increased spacing between shower head and susceptor; and also a susceptor having a diameter greater than the diameter of the wafer.
    Type: Grant
    Filed: April 6, 1993
    Date of Patent: April 12, 1994
    Assignee: AT&T Bell Laboratories
    Inventor: Chen-Hua D. Yu
  • Patent number: 5300461
    Abstract: Described is a structure and process for forming a hermetically sealed chip. This hermetically sealed chip will greatly simplify packaging requirements and eventually lead to the realization of a "packageless chip". The hermetic sealing is composed of two parts, an extremely thin passivation layer which is deposited over the entire chip top and side surfaces and a passivation layer which is deposited over the bonding pad surface. Preferably, SiN is deposited as a chip surface passivation layer and Ni is selectively deposited as a metal passivation layer. The extremely thin nitride layer will minimize the stress and the amount of hydrogen in the SiN film and minimize deleterious effects upon device performance caused by stress and hydrogen. The thickness of the metal passivation layer may be the same as that of the dielectric layer so as to give a planar surface or it may be thick enough so as to give a protruding metal passivation bump.
    Type: Grant
    Filed: January 25, 1993
    Date of Patent: April 5, 1994
    Assignee: Intel Corporation
    Inventor: Chiu H. Ting
  • Patent number: 5296211
    Abstract: The present invention relates to a process for the production of low-needle silicon nitride of high .alpha.-content, wherein an amorphous nitrogen-containing silane compound is mixed with a crystalline or amorphous compound comprising the elements silicon, phosphorus and nitrogen to form a mixture which is heat-treated at temperatures above 1000.degree. C. to form the low-needle silicon nitride. The present invention also relates to the silicon-, nitrogen- and phosphorus-containing compound which is used as the starting material in the process for the production of the low-needle silicon nitride, and the process for the production of the silicon-, nitrogen- and phosphorus-containing compound.
    Type: Grant
    Filed: January 6, 1993
    Date of Patent: March 22, 1994
    Assignee: Bayer AG
    Inventors: Hans-Peter Baldus, Wolfgang Schnick
  • Patent number: 5128116
    Abstract: The invention relates to a method for continuous production of silicon powder comprising the combination of the following steps:a) continuous production of silicon in an electric smelting furnace,b) refining and alloying of the molten silicon in a metal treatment vessel,c) continuous supply of modern silicon from the metal treatment vessel to a holding furnace,d) continuous supply of molten silicon to a closed atomizing apparatus wherein the molten silicon is atomized by means of an inert gas supplied from a pressure vessel or a compressor unit,e) continuous removal of atomized silicon powder from the atomizing apparatus,f) separation of atomized silicon powder and inert gas in a solid/gas separator,g) screening of the silicon powder into preset particle size fractions,h) supply of the different particle size fractions of silicon powder to closed product silos,i) filtration of the inert gas from step f) for removing any remaining solid particles from the inert gas,cooling and compressing the inert gas from st
    Type: Grant
    Filed: January 11, 1990
    Date of Patent: July 7, 1992
    Assignee: Elkem a/s
    Inventors: Karl Forwald, Gunnar Schussler, Oyvind Sorli
  • Patent number: 5039625
    Abstract: A Maximum Areal Density Recessed Oxide Isolation (MADROX) process for forming semiconductor devices, in which forms an insulating layer is formed on a monocrystalline silicon substrate and a patterned polycrystalline silicon-containing layer is formed on the insulating layer. The substrate is then subjected to a low temperature plasma assisted oxidation to form recessed oxide isolation areas in the exposed regions of the substrate, with minimal encroachment under the patterned polycrystalline silicon-containing layer. The patterned polycrystalline silicon-containing layer acts as a mask, without itself being oxidized. Low temperature recessed oxide isolation regions may thereby be formed, without "bird's beak" formation. Maximum Areal Density Bipolar and Field Effect Transistor (MADFET) devices may be formed, using the patterned polycrystalline silicon-containing layer as a device contact if desired.
    Type: Grant
    Filed: April 27, 1990
    Date of Patent: August 13, 1991
    Assignee: MCNC
    Inventors: Arnold Reisman, Mark Kellam, Charles K. Williams, Nandini Tandon
  • Patent number: 5024955
    Abstract: A variable-capacitance diode element is disclosed which comprises a semiconductor substrate of a first conductivity type having an epitaxial layer of the first conductivity type provided on a main surface portion thereof, said epitaxial layer having a higher resistivity than that of said semiconductor substrate; a first diffusion layer of the first conductivity type diffused in said epitaxial layer and having a lower resistivity than that of said epitaxial layer; a second diffusion layer of a second conductivity type surrounded by said first diffusion layer and having a lower resistivity than that of said first diffusion layer; and a third diffusion layer of the second conductivity type of a small diffusion length covering an exposed portion of a major surface of said first diffusion layer and an exposed portion of a major surface of said second diffusion layer. With such construction, the capacitance variation range of the diode element is widened, and the high-frequency serial resistance R.sub.
    Type: Grant
    Filed: June 13, 1990
    Date of Patent: June 18, 1991
    Assignee: Toko, Inc.
    Inventor: Takeshi Kasahara