Abstract: A transistor device and method of fabrication are provided, where the transistor device may include a semiconductor substrate, a first dielectric layer disposed on a surface of the semiconductor substrate, a second dielectric layer disposed directly on the first dielectric layer, a gate structure disposed directly on the surface of the semiconductor substrate, and a spacer structure. A first opening through the first dielectric layer and the second dielectric layer may correspond to a gate channel. Portions of the first dielectric layer and the second dielectric layer may be interposed directly between portions of the gate structure and the surface of the semiconductor substrate. The spacer structure may be disposed in the gate channel and interposed between the gate structure and the semiconductor substrate. The spacer structure may contact respective side surfaces of the first dielectric layer and the second dielectric layer that at least partially define the gate channel.

Abstract: To provide a method of manufacturing a display device capable of high resolution. A first EL layer, a first layer, and a second layer are formed over a first pixel electrode; a second EL layer, a third layer, and a fourth layer are formed over the second pixel electrode; a resin layer covering an end portion of the second layer and an end portion of the fourth layer is formed by applying a photosensitive resin, exposing the photosensitive resin to light, and developing the photosensitive resin; a top surface of the first EL layer and a top surface of the second EL layer are exposed by etching parts of the first layer, the second layer, the third layer, and the fourth layer which are not covered with the resin layer; and a common electrode covering the first EL layer, the second EL layer, and the resin layer are formed.

Abstract: A metal chalcogenide material layer of lower quality provides a transition between a metal chalcogenide material layer of higher quality and a gate insulator material that separates the metal chalcogenide material layers from a gate electrode of a metal-oxide semiconductor field effect transistor (MOSFET) structure. Gate insulator material may be more readily initiated and/or or precisely controlled to a particular thickness when formed on lower quality metal chalcogenide material. Accordingly, such a material stack may be integrated into a variety of transistor structures, including multi-gate, multi-channel nanowire or nanosheet transistor structures.

Abstract: Peak concentration of the carrier accumulation layer is equal to or higher than 1.0E16/cm3. A bottom part of the trench is positioned inside the n-type carrier accumulation layer. When a concentration ratio is a result of division of a concentration of the carrier accumulation layer by a concentration of the drift layer at a depth of the bottom part of the trench, the depth of the bottom part of the trench is a position at which the concentration ratio is larger than one and equal to or smaller than 10.

Abstract: A method for manufacturing a capacitive device comprising the following steps: a) providing a metallic layer, b) depositing a full-sheet aluminium layer, c) structuring pores in the aluminium layer by a full-sheet anodic etching process, subsequently to which a continuous porous alumina layer is obtained comprising a first main face and a second main face, longitudinal pores extending from the first main face to the second main face, d) forming a capacitive area at a first area of the porous alumina layer, e) forming an upper electrode over the capacitive area, f) forming a contact resumption at a second area of the porous alumina layer, g) forming a lower electrode over the contact resumption.

Abstract: The present application provides a method for making gates of different sizes compatible with the double patterning technology, comprising: forming a plurality of dummy gate structures and spacers on the sidewalls; covering the spacers and a region of large-sized gates with an SOC(silicon-on-carbon) layer; etching the SOC layer to expose the spacers of at least one dummy gate structure; respectively forming the first and the second SOC pattern structures, wherein the first SOC pattern structure covers the spacer of at least one dummy gate structure, and the second SOC pattern structure is disposed in region of the large-sized gates; etching the first SOC pattern structure to form a third SOC pattern structure, one side of the third SOC pattern structure covers one side of the spacer, wherein the other uncovered side of the spacer is used to define one side of the gate of medium-sized width.