Patents Examined by Kenneth Tsang
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Patent number: 9858193Abstract: A computer-implemented method, computer program product and computing system for defining a cache storage portion within a cache storage device coupled to a computing device. An application storage portion is defined within the cache storage device coupled to the computing device. The cache storage portion is configured to store cache data and the application storage portion is configured to store application data.Type: GrantFiled: May 13, 2016Date of Patent: January 2, 2018Assignee: EMC IP Holding Company LLCInventors: Roy E. Clark, Randall H. Shain, Barry Ader, Daniel S. Cobb
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Patent number: 9817756Abstract: Techniques are described for enabling a virtual machine to be presented with an amount of available guest memory, where a hypervisor or other privileged component manages the mapping of the guest memory to either volatile memory (e.g., RAM) or to secondary storage (e.g., SSD). This enables volatile memory to be effectively oversubscribed to on host computing devices that have a limited amount of total available volatile memory but which are running multiple virtual machines. For example, each virtual machine on the device can be presented as having access to the total amount of available RAM that is available on the device. The hypervisor or other virtualization component then monitors the usage of the memory by each virtual machine and shapes which portions of the guest memory for that virtual machine are mapped to RAM and which portions are mapped to secondary storage, such as SSD.Type: GrantFiled: May 23, 2013Date of Patent: November 14, 2017Assignee: AMAZON TECHNOLOGIES, INC.Inventor: Atle Normann Jorgensen
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Patent number: 9740632Abstract: In one aspect, a method includes receiving a request to write to an offset in a first logical device, determining a second logical device that wrote to the offset, the second logical device being an ancestor of the first logical device in a hierarchical tree of snapshots, determining from decedents of the second logical device in the hierarchical tree whether data in the offset of the second logical device is shadowed data or partially shadowed data, removing address-to-hash mapping for the offset of the second logical device if the data for the offset is shadowed and moving address-to-hash mapping to a single descendent of the second logical device if the data for the offset is partially shadowed.Type: GrantFiled: September 25, 2014Date of Patent: August 22, 2017Assignee: EMC IP HOLDING COMPANY LLCInventors: Phil Love, Kirill Shoikhet, Renen Hallak, Ido Halevi, Irit Lempel
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Patent number: 9703723Abstract: In an environment in which a processor operates a hypervisor and multiple guest partitions operating under the hypervisor's control, it is desirable to allow a guest partition access to a physical memory device without decreasing system performance. Accordingly, a conversion instruction for converting a logical address to a real address, i.e., an LTOR instruction, executable from a guest partition, is added to the processor. Upon the guest partition's execution of the conversion instruction with the logical address specified, the processor converts the logical address to an encrypted real address, and returns it to the guest partition. The guest partition is then able to pass the encrypted real address to an accelerator that converts the encrypted real address to a real address in order to access the memory device using the real address.Type: GrantFiled: July 9, 2012Date of Patent: July 11, 2017Assignee: International Business Machines CorporationInventors: Masanori Mitsugi, Hiroyuki Tanaka
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Patent number: 9535611Abstract: A method for data storage in a data storage system, which includes a main storage device and a non-volatile memory, includes assessing quality levels of respective memory blocks of the non-volatile memory. One or more of the memory blocks whose assessed quality levels are lower than a predefined quality threshold are identified. The identified memory blocks are assigned to serve as read cache memory. Data is read from the main storage device via the read cache memory, including the assigned memory blocks.Type: GrantFiled: May 20, 2016Date of Patent: January 3, 2017Assignee: Apple Inc.Inventor: Avraham Meir
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Patent number: 9529724Abstract: Approaches for implementing a controller for a hybrid memory that includes a main memory and a cache for the main memory are discussed. The controller comprises a hierarchy of abstraction layers, wherein each abstraction layer is configured to provide at least one component of a cache management structure. Each pair of abstraction layers utilizes processors communicating through an application programming interface (API). The controller is configured to receive incoming memory access requests from a host processor and to manage outgoing memory access requests routed to the cache using the plurality of abstraction layers.Type: GrantFiled: July 6, 2012Date of Patent: December 27, 2016Assignee: SEAGATE TECHNOLOGY LLCInventors: Sumanth Jannyavula Venkata, James David Sawin, Yunaldi Yulizar, Ryan James Goss
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Patent number: 9459806Abstract: For combining virtual mapping metadata and physical space mapping metadata in a storage system by a processor device in a computing environment, data and metadata are maintained into separate virtual streams. The separate virtual streams include a metadata stream for the metadata and a data stream for the data. Metadata for each input/output (I/O) operation received is determined using a linear function operation, the function operation being an offset of the metadata in the metadata stream that is equal to the I/O operation multiplied by a maximal metadata ratio. The metadata is allocated on the metadata stream and the metadata stream is divided into fixed size block that is responsible for describing a size of a logical space, where the logical space is equal to one divided by the maximal metadata ratio, and it is determined if the metadata has been previously loaded.Type: GrantFiled: April 28, 2016Date of Patent: October 4, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yuval Berger, Ben Sasson, Ori Shalev, Yosef Shatsky
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Patent number: 9454493Abstract: Systems and methods for verifying the wiping of a storage device using one of either a partial scan verification or a full scan verification, wherein a partial scan verification may be conducted based on at least one metric associated with the storage device and a threshold value for the at least one metric.Type: GrantFiled: May 4, 2012Date of Patent: September 27, 2016Assignee: Amazon Technologies, Inc.Inventor: Eden G. Adogla
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Patent number: 9430367Abstract: A first RAID module is added to a first RAID controller and a second RAID module is added to a second RAID controller. An array of physical disks is partitioned into two partitions across the array of physical disks. The first partition is assigned to the first RAID module and the second partition is exposed to the second RAID module. Each of the RAID modules exposes their respective partitions to their associated RAID controller as a single array. Each RAID module further receives I/O from its respective RAID controller, and translates the I/O to access its associated partition.Type: GrantFiled: April 18, 2012Date of Patent: August 30, 2016Assignee: AMERICAN MEGATRENDS, INC.Inventors: Srikumar Subramanian, Senthilkumar Ramasamy, Loganathan Ranganathan, Udita Chatterjee
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Patent number: 9405706Abstract: A processor includes a front end, a cache, and a cache controller. The front end includes logic to receive an instruction defining a priority dataset. The priority dataset includes ranges of memory addresses each corresponding to a respective priority level. The cache controller includes logic to detect a miss in the cache for a requested cache value, determine a candidate cache victim from the cache, determine a priority of the requested cache value and the candidate cache victim according to the priority dataset, and evict the candidate cache victim based on a determination that the priority of the candidate cache victim is less or equal to the priority of the requested cache value.Type: GrantFiled: September 25, 2014Date of Patent: August 2, 2016Assignee: Intel CorporationInventors: Kshitij A. Doshi, Karthik Raman, Christopher J. Hughes
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Patent number: 9372804Abstract: A method for data storage in a data storage system, which includes a main storage device and a non-volatile memory, includes assessing quality levels of respective memory blocks of the non-volatile memory. One or more of the memory blocks whose assessed quality levels are lower than a predefined quality threshold are identified. The identified memory blocks are assigned to serve as read cache memory. Data is read from the main storage device via the read cache memory, including the assigned memory blocks.Type: GrantFiled: July 13, 2015Date of Patent: June 21, 2016Assignee: Apple Inc.Inventor: Avraham Meir
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Patent number: 9372803Abstract: A system and method are presented. Some embodiments include a processing unit, at least one memory coupled to the processing unit, and at least one cache coupled to the processing unit and divided into a series of blocks, wherein at least one of the series of cache blocks includes data identified as being in a modified state. The modified state data is flushed by writing the data to the at least one memory based on a write back policy and the aggressiveness of the policy is based on at least one factor including the number of idle cores, the proximity of the last cache flush, the activity of the thread associated with the data, and which cores are idle and if the idle core is associated with the data.Type: GrantFiled: December 20, 2012Date of Patent: June 21, 2016Assignee: Advanced Micro Devices, Inc.Inventors: Srilatha Manne, Michael Schulte, Lloyd Bircher, Madhu Saravana Sibi Govindan, Yasuko Eckert
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Patent number: 9367453Abstract: A computer-implemented method, computer program product and computing system for moving at least a portion of cache data from a first cache storage device coupled to a first computing device included within a first virtual machine to a shared storage device. The at least a portion of cache data is moved from the shared storage device to a second cache storage device coupled to a second computing device included within a second virtual machine.Type: GrantFiled: September 30, 2011Date of Patent: June 14, 2016Assignee: EMC CorporationInventors: Roy E. Clark, Randall H. Shain, Robert W. Beauchamp, Michel F. Fisher
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Patent number: 9367452Abstract: A computer-implemented method, computer program product and computing system for defining a cache storage portion within a cache storage device coupled to a computing device. An application storage portion is defined within the cache storage device coupled to the computing device. The cache storage portion is configured to store cache data and the application storage portion is configured to store application data.Type: GrantFiled: September 30, 2011Date of Patent: June 14, 2016Assignee: EMC CorporationInventors: Roy E. Clark, Randall H. Shain, Barry Ader, Daniel S. Cobb
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Patent number: 9335942Abstract: Methods and structure for masking of logical unit numbers (LUNs) within a switching device coupled with one or more storage enclosures. Each storage enclosure defines one or more logical volumes each identified by a LUN within the storage enclosures. The switching device gathers LUN definition information regarding each LUN defined by each storage enclosure coupled with the switching device. LUN access permission information may be provided by an administrative node/user defining a level of access permitted or denied for each host system for each LUN for each storage enclosure. The switching device then intercepts a REPORT LUNS command from any host directed to a storage enclosure and responds with only those LUNs to which the requesting host system has permitted access. Further, any other SCSI command intercepted at the switching device directed to a LUN to which the host system does not have access is modified to identify an invalid LUN.Type: GrantFiled: April 18, 2012Date of Patent: May 10, 2016Assignee: Avago Technologies General IP (Technologies) Pte. Ltd.Inventors: Umang Kumar, Nishant Kumar Yadav, Abhijit Suhas Aphale
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Patent number: 9329780Abstract: For combining virtual mapping metadata and physical space mapping metadata in a storage system by a processor device in a computing environment, data and metadata are maintained into separate virtual streams. The separate virtual streams include a metadata stream for the metadata and a data stream for the data. Information of a mapping of logical data to a location on the data stream and a current state of unused spaces in the data stream is linearly distributed within the metadata stream.Type: GrantFiled: February 11, 2014Date of Patent: May 3, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yuval Berger, Ben Sasson, Ori Shalev, Yosef Shatsky
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Patent number: 9317217Abstract: Systems and methods for wiping and verifying the wiping of a data storage device where the dirtying of blocks of the storage device is tracked and only the dirtied blocks are scanned to verify if the storage device has been sufficiently wiped.Type: GrantFiled: May 4, 2012Date of Patent: April 19, 2016Assignee: Amazon Technologies, Inc.Inventor: Eden G. Adogla
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Patent number: 9294529Abstract: An embodiment for reusing data in content files includes receiving a request for a content file and retrieving a recipe that includes a series of instructions needed to compose the content file. Data identified by the recipe may then be retrieved from a content file server and the requested content file is composed based on the set of instructions in the recipe. In an example, the recipe is processed by a recipe player to compose a content file. In another embodiment, content files are stored in a cache as a series of instructions for generating them from portions of other content files. In this way, performance in a content delivery network may be improved by reusing similar data in content files.Type: GrantFiled: September 1, 2015Date of Patent: March 22, 2016
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Patent number: 9244846Abstract: A data processing system implements a weak consistency memory model for a distributed shared memory system. The data processing system concurrently executes, on a plurality of processor cores, one or more transactional memory instructions within a memory transaction and one or more non-transactional memory instructions. The one or more non-transactional memory instructions include a non-transactional store instruction. The data processing system commits the memory transaction to the distributed shared memory system only in response to enforcement of causality of the non-transactional store instruction with respect to the memory transaction.Type: GrantFiled: July 6, 2012Date of Patent: January 26, 2016Assignee: International Business Machines CorporationInventors: Bradly G. Frey, Cathy May, Derek E. Williams
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Patent number: 9160776Abstract: An embodiment for reusing data in content files includes receiving a request for a content file and retrieving a recipe that includes a series of instructions needed to compose the content file. Data identified by the recipe may then be retrieved from a content file server and the requested content file is composed based on the set of instructions in the recipe. In an example, the recipe is processed by a recipe player to compose a content file. In another embodiment, content files are stored in a cache as a series of instructions for generating them from portions of other content files. In this way, performance in a content delivery network may be improved by reusing similar data in content files.Type: GrantFiled: July 16, 2012Date of Patent: October 13, 2015