Abstract: A method of fabricating a phase change RAM (PRAM) having a fullerene layer is provided. The method of fabricating the PRAM may include forming a bottom electrode, forming an interlayer dielectric film covering the bottom electrode, and forming a bottom electrode contact hole exposing a portion of the bottom electrode in the interlayer dielectric film, forming a bottom electrode contact plug by filling the bottom electrode contact hole with a plug material, forming a fullerene layer on a region including at least an upper surface of the bottom electrode contact plug and sequentially stacking a phase change layer and an upper electrode on the fullerene layer. The method may further include forming a switching device on a substrate and a bottom electrode connected to the switching device, forming an interlayer dielectric film covering the bottom electrode and forming a bottom electrode contact hole exposing a portion of the bottom electrode in the interlayer dielectric film.

Abstract: After protective insulating films are formed on first to third active regions, the protective insulating films formed on the first and third active regions are removed. Subsequently, an insulating film to be a first gate insulating film is formed on each of the first and third active regions, and then, the protective insulating film formed on the second active region is removed. Next, an insulating film to be a second gate insulating film is formed on the second active region, and then, the insulating film to be the first gate insulating film formed on the third active region is removed. Finally, an insulating film to be a third gate insulating film is formed on the third active region.

Abstract: A method is provided for fabricating a semiconductor device which includes a first contact point and a second contact point located above the first contact point. A first material layer is conformally deposited over the contact points, and a second material layer is deposited. A photoresist layer is applied and patterned to leave remaining portions. The remaining portions are trimmed to produce trimmed remaining portions which overlie eventual contact holes to the contact points. Using the trimmed remaining portions as an etch mask, exposed portions the second material layer are etched away to leave sacrificial plugs. The sacrificial plugs are etched away to form contact holes that reach portions the first material layers. Another etching step is performed to extend the contact holes to produce final contact holes that extend to the contact points.

Abstract: The memory device includes a source region and a drain region in a substrate and spaced apart from each other; a memory cell formed on a surface of the substrate, wherein the memory cell connects the source region and the drain region and includes a plurality of nanocrystals; a control gate formed on the memory cell. The memory cell includes a first tunneling oxide layer formed on the substrate; a second tunneling oxide layer formed on the first tunneling oxide layer; and a control oxide layer formed on the second tunneling oxide layer. The control oxide layer includes the nanocrystals. The second tunneling oxide layer, having an aminosilane group the increases electrostatic attraction, may be hydrophilic, enabling the formation of a monolayer of the nanocrystals.

Abstract: A method for achieving uniaxial strain on originally biaxial-strained thin films after uniaxial strain relaxation induced by ion implantation is provided. The biaxial-strained thin film receives ion implantation after being covered by a patterned implant block structure. The strain in the uncovered region is relaxed by ion implantation, which induces the lateral strain relaxation in the covered region. When the implant block structure is narrow (dimension is comparable to the film thickness), the original biaxial strain will relax uniaxially in the lateral direction.

Abstract: According to an example embodiment, a semiconductor device includes a lower electrode (316) disposed on an oxide layer (302), an upper electrode (320) disposed on the lower electrode, a dielectric pattern (322) disposed on the oxide layer and surrounding the upper electrode, the upper electrode protruding above an upper surface of the dielectric pattern, and a contact pattern (328) that is contiguous with the upper electrode and the dielectric pattern.

Abstract: A method for manufacturing a semiconductor device, the method including the steps of: (a) forming a titanium layer above a substrate; (b) forming a barrier layer above the titanium layer; (c) changing the titanium layer to a titanium nitride layer by conducting a heat treatment in a nitrogen containing atmosphere; (d) forming a first electrode above the barrier layer; (e) forming a ferroelectric layer above the first electrode; and (f) forming a second electrode above the ferroelectric layer.

Abstract: Some embodiments include methods of forming a NAND cell unit having a NAND string gate closest to a select gate with a different width than other NAND string gates more distant from the select gate. Some embodiments include utilization of an etch comprising HBr and O2 to extend a pattern through a carbon-containing layer. The patterned carbon-containing layer may be used to pattern NAND cell unit gates. Some embodiments include structures having a patterned carbon-containing layer defining a NAND cell unit having a NAND string gate closest to a select gate with a different width than other NAND string gates more distant from the select gate.

Abstract: The invention provides methods and systems for laser assisted wirebonding. One or more conditioning laser pulses are used to prepare a bonding surface for wirebonding by removing impurities such as residues from manufacturing processes, oxides, or irregularities on the bonding surface. Subsequently, a free air ball is brought into contact with the conditioned bonding surface to form a weld.

Abstract: Methods of forming capacitor-free DRAM cells include forming a field effect transistor by forming a first semiconductor wafer having a channel region protrusion extending therefrom and surrounding the channel region protrusion by an electrical isolation region. A portion of a backside of the first semiconductor wafer is then removed to define a semiconductor layer having a primary surface extending opposite the channel region protrusion and the electrical isolation region. A gate electrode is formed on the primary surface. The gate electrode extends opposite the channel region protrusion. The source and drain regions are formed in the semiconductor layer, on opposite sides of the gate electrode.

Abstract: A packaging substrate and a manufacturing method thereof are provided. The manufacturing method includes following steps. First, a first packaging substrate including several first substrate units and at least one defected substrate unit is provided. Next, the defected substrate unit is separated from the packaging substrate, and at least one opening is formed in a frame of the first packaging substrate correspondingly. Then, a second substrate unit is provided. The shape of the second substrate unit is different from the shape of the opening. Afterwards, the second substrate unit is disposed in the opening.

Abstract: A method of making a semiconductor device includes a substrate having a semiconductor layer having a first portion for non-volatile memory and a second portion exclusive of the first portion. A first dielectric layer is formed on the semiconductor layer. A plasma nitridation is performed on the first dielectric layer. A first plurality of nanoclusters is formed over the first portion and a second plurality of nanoclusters over the second portion. The second plurality of nanoclusters is removed. A second dielectric layer is formed over the semiconductor layer. A conductive layer is formed over the second dielectric layer.

Abstract: A method for preparing a microelectromechanical system (MEMS) device for subsequent processing is disclosed. The method includes establishing an anti-stiction material on exposed surfaces of the MEMS device. The exposed surfaces include at least an interior surface of a chamber and an external surface of the MEMS device. The anti-stiction material is selectively removed from at least a portion of the external surface via a plasma sputtering process under controlled conditions.

Abstract: A method for forming a thin film of a semiconductor device is provided. The method includes forming a TaN film on a semiconductor substrate, and converting a portion of the TaN film into a Ta film by reacting the TaN film with NO2. The Ta film is formed to have a thickness which is about half of the thickness of the TaN film.

Abstract: A method for manufacturing a coreless packaging substrate is disclosed. The method can produce a coreless packaging substrate which comprises: at least a built-up structure having a first solder mask and a second solder mask, wherein a plurality of openings are formed in the first and second solder mask to expose the conductive pads of the built-up structure; and a plurality of solder bumps as well as solder layers formed on the conductive pads. Therefore, the invention can produce the coreless packaging substrate with high density of circuit layout, less manufacturing steps, and small size.

Abstract: A method for forming a thin film of a semiconductor device is provided. The method includes forming a TaN film on a semiconductor substrate by employing an atomic layer deposition method; and converting a part of the TaN film into a Ta by reacting the TaN film with NO2 to form a Ta film. The NO2 is formed by reacting NH3 with O2.

Abstract: A method of making a semiconductor device includes a substrate having a semiconductor layer having a first portion for non-volatile memory and a second portion exclusive of the first portion. A first dielectric layer is formed over the semiconductor layer. A first plurality of nanoclusters is formed over the first portion and a second plurality of nanoclusters is formed over the second portion. A layer of nitrided oxide is formed around each nanocluster of the first plurality and the second plurality of nanoclusters. Remote plasma nitridation is performed on the layers of nitrided oxide of the first plurality of nanoclusters. The nanoclusters are removed from the second portion. A second dielectric layer is formed over the semiconductor layer. A conductive layer is formed over the second dielectric layer.

Abstract: A method of manufacturing a well pick-up structure of a non-volatile memory is provided. A substrate including a first conductive type well, device isolation structures and dummy memory columns is provided. Each of the dummy memory columns includes a second conductive type source region and a second conductive type drain region. A first interlayer insulating layer with an opening is formed over the substrate, and the opening exposes the two adjacent second conductive type drain regions and the device isolation structure between the two adjacent second conductive type drain regions. A portion of the device isolation structure exposed by the opening is removed, and then a first conductive type well extension doped region is formed in the substrate exposed by the opening. A well pick-up conductive layer is formed in the opening. Dummy bit lines electrically connecting the well pick-up conductive layer are formed over the substrate.

Abstract: A flip chip on leadframe package and manufacturing method includes providing a leadframe having a plurality of inner leads; providing a chip having an active surface; forming a plurality of first bumps and at least one second bump on the active surface, the material of the first bumps is the same as the second bump, and the height of the second bump is lower than the first bumps; dipping the top of the first bumps in a flux, so that the second bump is not dipped with the flux; contacting the first bumps to the corresponding inner leads; proceeding with a reflow so that the first bumps are melted and connected to the corresponding inner leads, and the second bump is connected to the corresponding inner lead without being melted, to maintain a gap between the chip and the inner leads to prevent collapse of the first bumps.

Abstract: A method of manufacturing a coreless packaging substrate is disclosed. The method can produce a coreless packaging substrate which comprises: at least a built-up structure having a first solder mask and a second solder mask, wherein a plurality of openings are formed in the first and second solder mask to expose the conductive pads of the built-up structure; and a plurality of solder bumps as well as solder layers formed on the conductive pads. Therefore, the invention can produce the coreless packaging substrate with high density of circuit layout, less manufacturing steps, and small size.