Abstract: A system for generating and storing trace bits for Viterbi decoding of binary convolution codes includes at least one arithmetic logic unit (ALU) for determining the trace bits, and a first register and a second register for storing the trace bits. The first register stores a first half of a series of trace bits for N states in sequential order and the second register stores a second half of the series in sequential order. A binary convolution decoder having multiple stages each having N states includes at least one arithmetic logic unit (ALU), a first register and a second register, and a storage device. The at least one ALU determines trace bits for each of the N states for each of the multiple stages. The first and second registers store trace bits of at least a portion of one stage. The storage device has memory cells. For each of the multiple stages, a group of at least one memory cell stores the N trace bits in sequential order.

Abstract: Disclosed are a method and an apparatus to estimate a signal-to-noise ratio (SNR) of a signal. The method includes sampling the signal, correlating and channel estimating the sampled signal, symbol combining the correlated and channel estimated signal, such as by using a maximal-ratio combining technique, estimating pilot channel and noise power to obtain a combined pilot power and noise variance estimate and inputting the symbol combined signal and the pilot power and noise variance estimate to an Eb/Nt (SNR) estimator. The method further includes, in the Eb/Nt estimator, subtracting a noise term, multiplied by a constant, from the combined signal power and computing a ratio of the unbiased signal power to the noise power to obtain an unbiased (Eb/Nt) estimate.

Abstract: According to the present invention, methods and apparatus are provided for improving the signal quality of received transmission. An adaptive equalizer includes multiple output delay lines. One output delay line is configured to provide gradient elements. Another output delay line is configured with coefficient multipliers calculated using the gradient elements. The coefficient multipliers are used to alter a received signal to more closely correspond to an expected signal. The adaptive equalizer can be used in systems such as optical transceivers.

Abstract: A GPS receiver acquires carrier frequency and Gold code phase using short segments of a received GPS signal. In one embodiment, a 1-ms segment of the GPS signal is transformed to the frequency domain. This is multiplied by a frequency representation of the Gold code. The resulting product is converted to the time domain, and a peak is detected. The location of the peak corresponds to the code phase. If no peak is located, the carrier frequency is changed. Full- and half-bin steps in carrier frequency are considered. Processing gain is achieved by using longer segments of the input signal, for example 4 or 16 ms and integrating 1-ms segments. Considerations are provided for compensating for the effects of a transition, should it occur in the short segment of the GPS signal being processed. Integrations can be performed using non-coherent and coherent techniques. Adjustments are made for non-integral millisecond segment lengths.

Abstract: The system and method of the preferred embodiments may be directed to improving the signal-to-noise ratio in frequency spectrum regions where narrowband interference may be present. The system and method of the preferred embodiments includes reducing the narrowband interference by determining a noise estimate. In accordance with the noise estimate and output of a frequency domain equalizer, a noise-cancelled output may be obtained.

Abstract: The number of pins on an integrated circuit chip is reduced by encoding control signals into a differential clock. The differential clock has two clock lines with complementary signals that together represent a clock. Control signals inside a clock-transmitting chip are input to an encoder which determines which control signal is being asserted or de-asserted. The encoder drives a clock-control signal that either forces both differential clock lines low or stops the differential clock from pulsing. A clock-receiving chip detects the both-low or stopped differential clock and determines which control signal was asserted or de-asserted. A phase-locked loop (PLL) in the receiver keeps an internal clock running even when the differential clock is missing pulses. A sequence of M1 missing clock pulses, followed by N1 clock pulses, followed by M2 missing pulses encodes the control signal, where M1, N1, and M2 are whole numbers.

Abstract: The invention provides a method and an arrangement which allow avoidance of significant degradation in performance of a broadband system receiver or even blocking of the receiver, caused by simultaneous use of the same frequency or simultaneous use of adjacent frequencies by a narrowband and a broadband communications systems, or background noise peaks produced by a plurality of various man-made interference signals. In one invention embodiment, the energy of the received signal is determined in narrower sub-bands, the average of the sub-band signal energies is calculated, the energies of the sub-band signals are compared with said average and if any of the sub-band signal energies exceeds the average by a predetermined threshold value, interference is cancelled by a tunable band-stop filter.

Abstract: A method and apparatus for automated correlation of digital modulation impairment is described. The technique obtains soft decision data (116, 2502) and extracts signal space location information of sufficient resolution to distinguish different types of impairment to a digitally modulated signal. The technique applies an error vector magnitude mask (117, 502) and determines the signal-to-noise ratio of the digitally modulated signal. The technique applies impairment masks (118, 2504) and provides a characterization (119) of impairment affecting the digitally modulated signal (112). The technique determines a subset of the soft decision data (116, 2502) that falls within the impairment masks (118, 2505) and calculates correlation weights (2506). The technique may be used to identify, isolate, and classify different types of impairment. Given sufficient data collection, sources of impairments may be determined precisely.

Abstract: A cross polarization interference canceller includes (a) first and second signal receivers which receive signals having been transmitted through first and second polarizations orthogonal with each other, (b) first and second local oscillators each of which converts one of the signals into an IF signal, (c) first and second demodulators each of which demodulates the IF signal for producing a base-band signal and a cross polarization interference cancel reference signal, (d) a phase-difference detector which detects a phase-difference between local signals transmitted from the first and second local oscillators, and transmits a phase-difference signal indicative of the thus detected phase-difference, and (e) first and second phase controllers associated with the first and second demodulators, respectively, and each equalizing phases of the base-band signal and the cross polarization interference cancel reference signal to each other in accordance with the phase-difference signal.

Abstract: A GPS receiver acquires carrier frequency and Gold code phase using short segments of a received GPS signal. In one embodiment, a 1-ms segment of the GPS signal is transformed to the frequency domain. This is multiplied by a frequency representation of the Gold code. The resulting product is converted to the time domain, and a peak is detected. The location of the peak corresponds to the code phase. If no peak is located, the carrier frequency is changed. Full- and half-bin steps in carrier frequency are considered. Processing gain is achieved by using longer segments of the input signal, for example 4 or 16 ms and integrating 1-ms segments. Considerations are provided for compensating for the effects of a transition, should it occur in the short segment of the GPS signal being processed. Integrations can be performed using non-coherent and coherent techniques.

Abstract: A wireless communication system transmits data on multiple carriers simultaneously to provide frequency diversity. Carrier interference causes a narrow pulse in the time domain when the relative phases of the multiple carriers are zero. Selection of the frequency separation and phases of the carriers controls the timing of the pulses. Both time division of the pulses and frequency division of the carriers achieves multiple access. Carrier interferometry is a basis from which other communication protocols can be derived. Frequency hopping and frequency shifting of the carriers does not change the pulse envelope if the relative frequency separation and phases between the carriers are preserved. Direct sequence CDMA signals are generated in the time domain by a predetermined selection of carrier amplitudes. Each pulse can be sampled in different phase spaces at different times. This enables communication in phase spaces that are not detectable by conventional receivers.

Abstract: A digital subscriber line transmission system using QAM modulation on several equally spaced discrete tones, uses, at a high transmission rate, N=2048/p or 4096/p tones spaced by 4.3125p KHz, where p is a power of 2.

Abstract: Methods and apparatus for feature recognition time shift correlation are presented. An exemplary method includes the step of identifying a feature in an input data stream. A starting time associated with the identified feature relative to a boundary of the input data stream is stored. A time interval until the identified feature is next repeated in the input data stream is then measured. Next, the measured time interval is compared to each of a set of valid interval values for the identified feature. A difference is then calculated between the stored starting time and a starting time associated with the identified feature relative to a boundary of a reference data sequence when the measured time interval matches one of the valid interval values. The calculated difference determines an amount that the input data stream must be time-shifted to achieve correlation with the reference data sequence.

Abstract: A transition between values of two successive bits is detected. The bit after the transition is used as one of the recovered bits. A recovery circuit may independently generate a sampling clock based on an analog signal, and sample the analog signal at time points specified by the sampling clock to generate multiple data bits. A multiplexor is used to provide a bit after the transition instead of a bit generated by the recovery circuit. As all bits after transition are recovered, data encoded in an analog signal may be recovered accurately.

Abstract: An improved digital capacitive isolation barrier system is provided that is suitable for use in a telephone or modem where the locally powered circuits must be effectively isolated from the public telephone system, while permitting data transfer across the barrier. In particular, an automatic ADC offset calibration system is provided for determining the magnitude of the ADC offset signal required in the system during a calibration operation, and for providing the calibrated ADC offset signal during normal operation of the isolation barrier system. A modified hybrid circuit is provided for isolating the system input from the telephone line during calibration, and for completing the calibration loop. Fixed bias signals are also provided for the ADC and for a DAC in the system. In a preferred embodiment, the ADC is located on the isolated side of the isolation barrier, while the integrator and register that determine and hold the offset signal are located on the powered side of the isolation barrier.

Abstract: An output circuit of the present invention includes a data output circuit and a clock output circuit. The output circuit includes a first D-type flip-flop and a selector for selectively outputting an output from the first D-type flip-flop or second data according to a selection signal. The clock output circuit includes a second D-type flip-flop, a third D-type flip-flop, and a dummy selector circuit. The dummy selector circuit is connected to the second and third D-type flip-flops and outputs a clock signal by using the same elements as those of the selector in order to realize the same delay time as that of the selector.

Abstract: A method and apparatus for extending the dynamic range of an integer or fixed-point Fast Fourier Transform (“FFT”) system that may be used in communications devices such as ADSL modems. The disclosed FFT system utilizes a shift control module to increase the effective dynamic range of the FFT implementation by selectively choosing at least one stage of an FFT butterfly implementation in which the outputs of the butterfly stage are not divided to otherwise avoid overflow problems.

Abstract: A transmitting circuit apparatus has a first digital modulator and a second digital modulator for modulating an I signal and a Q signal which are multi-valued digital baseband modulation signals, into a digital I signal and a digital Q signal, respectively, having the number of bits smaller than that of the baseband modulation signals; and a quadrature modulator for outputting a signal synthesized from the signals generated by modulating (two) carrier waves each having a phase perpendicular to each other by using the modulated I and Q signals, respectively.

Abstract: A phase of a sampling clock provided from clock generating circuit 107 is switched periodically and alternately with a phase difference of 180 degrees, and during a period of each phase, timing estimating circuit 105 estimates a symbol timing. High-accuracy timing estimating circuit 109 selects an estimated result with higher reliability among symbol timing estimated results obtained in respective periods, thereby enabling estimation of the symbol timing with time resolution twice a sampling period. It is possible to decrease an operation frequency in an A/D conversion circuit even in a system requiring timing synchronization accuracy with high accuracy.

Abstract: An equalizer operates on chip or sub-chip resolution input samples of a received spread-spectrum multipath signal to remove interference from one or more secondary propagation path signals within the multipath signal. The equalizer may be configured for cancellation of secondary signals arriving before and after a main propagation path signal. The length of sample delay buffers and the input sample rate determine the maximum secondary signal delay accommodated by the equalizer. The equalizer makes a hard-decision about the phase value of each input sample and buffers these hard-decision values for use in secondary signal cancellation. The hard-decision values are used to rotate the phase of corresponding path coefficients. These adjusted values are fed back for subtraction from input samples for post-cursor cancellation, and fed forward for subtraction from delayed input samples for pre-cursor cancellation.