Abstract: The principles of the present invention relate to a multiply and divide circuit configured to interactively multiply and/or divide. The circuit may handle signed and unsigned values. The circuit comprises an instruction register configured to store a multiply or divide instruction, at one input register configured to store the multiply or divide operands, an Arithmetic Logic Unit (“ALU”) configured to add provided values, and configuration circuitry. The configuration circuitry responds to the instructions and performs the multiply or divide operation by iteratively providing values to the ALU.

Abstract: One or more continuous mappings are defined at a digital media encoder to convert input digital media data in a first high dynamic range format to a second format with a smaller dynamic range than the first format. The encoder converts the input digital media data to the second format with the smaller dynamic range using the continuous mapping and one or more conversion parameters relating to the continuous mapping. The encoder encodes the converted digital media data in a bitstream along with the conversion parameter(s). The conversion parameter(s) enable a digital media decoder to convert the converted digital media data back to the first high dynamic range format from the second format with the smaller dynamic range. Techniques for converting different input formats with different dynamic ranges are described.

Abstract: Provided is a semiconductor integrated circuit and an exponent calculation method that, when normalizing a plurality of data by a common exponent, speed up exponent calculation and reduce circuit scale and power consumption. When normalizing a plurality of data by a common exponent, a semiconductor integrated circuit calculates the exponent of the plurality of data. Included is a bit string generator that generates a second bit string containing bits having a transition value indicating that values of adjacent bits are different or a non-transition value indicating that values of adjacent bits are not different for each pair of adjacent bits of a first bit string constituting the data, and an exponent calculator that calculates the exponent of the plurality of data based on bit position of the transition value of a plurality of second bit strings generated from a plurality of first bit strings respectively constituting the plurality of data.

Abstract: A method is provided for adding binary numbers, each of N bits, based on an accumulation mechanism which, for each iteration of index i+1 with I>0, generates an estimation signal Ui+1 on N bits and a correction signal Ri+1 on N bits, on the basis of a binary input number c, an estimation signal Ui and a correction signal Ri on N bits emanating from a previous iteration i. The estimation signal Ui and the correction signal Ri represent a sum of a least two binary numbers in redundant form. The estimation signal Ui+1 and the correction signal Ri+1 represent, in redundant form, the sum of the at least two binary numbers in redundant form and the binary number c. In other words, such a method makes it possible to sum a further binary number with a result represented in a redundant binary form of the type “U/R”, this result resulting from an initialization or a previous summation, and then to generate a result also in a redundant binary form of the type “U/R”.

Abstract: The invention discloses a method and controller for processing data multiplication in a RAID system. Map tables are generated for all values in a field, respectively. The length of an XOR operation unit is chosen to be appropriate w bits (e.g., 332 bits or 64 bits). One or several XOR operation units form a multiplication unit of a data sector. When computing on-line, data in a disk drive of a disk array are performed with XOR operations in accordance with one of the map tables using an XOR operation unit as one unit while computing on the multiplication unit to obtain a product of multiplication. Making use of the RAID system established according to the disclosed method, only XOR operations are required to compute parity data or recover damaged user data. Moreover, several calculations can be performed simultaneously. Therefore, the efficiency of the RAID system can be effectively improved.

Abstract: In general, techniques are described that provide for 4×4 transforms for media coding. A number of different 4×4 transforms are described that adhere to these techniques. As one example, an apparatus includes a 4×4 discrete cosine transform (DCT) hardware unit. The DCT hardware unit implements an orthogonal 4×4 DCT having an odd portion that applies first and second internal factors (C, S) that are related to a scaled factor (?) such that the scaled factor equals a square root of a sum of a square of the first internal factor (C) plus a square of the second internal factor (S). The 4×4 DCT hardware unit applies the 4×4 DCT implementation to media data to transform the media data from a spatial domain to a frequency domain. As another example, an apparatus implements a non-orthogonal 4×4 DCT to improve coding gain.

Abstract: A method, system, and processor-readable storage medium are directed towards calculating approximate order statistics on a collection of real numbers. In one embodiment, the collection of real numbers is processed to create a digest comprising hierarchy of buckets. Each bucket is assigned a real number N having P digits of precision and ordinality O. The hierarchy is defined by grouping buckets into levels, where each level contains all buckets of a given ordinality. Each individual bucket in the hierarchy defines a range of numbers—all numbers that, after being truncated to that bucket's P digits of precision, are equal to that bucket's N. Each bucket additionally maintains a count of how many numbers have fallen within that bucket's range. Approximate order statistics may then be calculated by traversing the hierarchy and performing an operation on some or all of the ranges and counts associated with each bucket.

Abstract: A method, system, and processor-readable storage medium are directed towards calculating approximate order statistics on a collection of real numbers. In one embodiment, the collection of real numbers is processed to create a digest comprising hierarchy of buckets. Each bucket is assigned a real number N having P digits of precision and ordinality O. The hierarchy is defined by grouping buckets into levels, where each level contains all buckets of a given ordinality. Each individual bucket in the hierarchy defines a range of numbers—all numbers that, after being truncated to that bucket's P digits of precision, are equal to that bucket's N. Each bucket additionally maintains a count of how many numbers have fallen within that bucket's range. Approximate order statistics may then be calculated by traversing the hierarchy and performing an operation on some or all of the ranges and counts associated with each bucket.

Abstract: Disclosed herein are systems and methods for a signed-magnitude adder based on one's complement logic, where the adder offers enhancements in both speed and chip area consumption. The one's complement based adder includes circuitry for converting operands from their signed-magnitude representations to their one's complement representations, circuitry for adding operands in their one's complement representations, and circuitry for converting the resulting sum into a signed-magnitude format.

Abstract: In one embodiment, the present invention includes a method for receiving a reciprocal instruction and an operand in a processor, accessing an entry of a lookup table based on a portion of the operand and the instruction, generating an encoder output based on a type of the reciprocal instruction and whether the reciprocal instruction is a legacy instruction, and selecting portions of the lookup table entry and input operand to be provided to a reciprocal logic unit based on the encoder output. Other embodiments are described and claimed.

Abstract: An algorithm system to detect a broad class of signals in Gaussian noise using higher-order statistics. The algorithm system detects a number of different signal types. The signals may be in the base-band or the pass-band, single-carrier or multi-carrier, frequency hopping or non-hopping, broad-pulse or narrow-pulse etc. In a typical setting this algorithm system provides an error rate of 3/100 at a signal to noise ratio of 0 dB. This algorithm system gives the time frequency detection ratio that may be used to determine if the detected signal falls in Class Single-Carrier of Class Multi-Carrier. Additionally this algorithm system may be used for a number of different applications such as multiple signal identification, finding the basis functions of the received signal and the like.

Abstract: A processing apparatus comprising a register that stores operand data, a register data reading section that reads operand data stored in the register, a coefficient table set storage section that stores a coefficient table storing Taylor series operation coefficient data, a coefficient data reading section that reads the Taylor series coefficient data from the coefficient table set storage section using the degree information of the Taylor series and the coefficient table identification information and a floating point multiply-adder that executes the Taylor series operation using the coefficient data read by the coefficient data reading section, data read from the register.

Abstract: A data converting method and device therefor are disclosed by the invention, relating to data converting algorithm field, solving the problem of complicate data converting method in prior art. Steps of the invention are obtaining offset from the predetermined byte of the data string to be converted; obtaining the predetermined bits of data from the data string to be converted according to the offset; converting the obtained bits to decimal number; determining whether size of the decimal number is smaller than the first predetermined length, if so, keeping adding 0 to the upper digit of the decimal number till the first predetermined length is reached, and taking the data with added 0 as the converted data; otherwise keeping obtaining data from low bit of the decimal number, till the first predetermined length is reached, and taking the obtained data as the converted data. The method of the invention is mainly used for devices and methods requiring data converting, e.g.

Abstract: An apparatus having a carryless preformat unit, a Booth encoder, a compressor, a left shifter, and exclusive-OR logic. The carryless preformat unit receives a multiplier operand and partitions the multiplier operand into parts. The Booth encoder receives the parts and directs selection of first partial products of a multiplicand that do not reflect implicit carry operations. The compressor sums the first partial products via a configuration of carry save adders that generate sum bits and carry bits, where generation of the carry bits is disabled during execution of the carryless multiplication. The left shifter shifts bits of one or more outputs of the compressor. The exclusive-OR logic is coupled to the compressor and the left shifter, and is configured to execute an exclusive-OR function on the outputs to yield a carryless multiplication result.

Abstract: A read channel of a magnetic data storage device includes a filter to provide equalization of the signal being detected from the magnetic media. The filter utilizes coefficients for the filter response. The filter coefficients may drift sideways over time. The drift is detected and a correction is implemented by imposing a leakage on the coefficients to re-center the filter response. The leakage sign differs depending on the direction of drift detected.

Abstract: We describe a method for using a classical computer to generate a sequence of elementary operations (SEO) that can be used to operate a quantum computer. A quantum computer operating under such a SEO can be used to evaluate certain quantum operator averages.

Abstract: Techniques for performing IFFT pipelining are described. In some aspects, the pipelining is achieved with a processing system having a memory having first and second sections, an encoder configured to process data in each of the first and second memory sections, an IFFT configured to process the encoded data in the first and second memory sections, and a post-processor configured to process the IFFT processed data in the first memory section while the IFFT is processing the encoded data in the second memory section, the post processor configured to operate at a different clock speed than the encoder or the IFFT.

Abstract: A system includes a first powered apparatus having a first analog signal with a fundamental frequency; and a second apparatus providing load diagnostics or power quality assessment of the first apparatus from a second digital signal. The second apparatus includes an input of the first analog signal, an output of the second digital signal, a processor, an adaptive filter executed by the processor, a digital-to-analog converter, and an analog-to-digital converter. The adaptive filter routine outputs a third digital signal as a function of the second digital signal and plural adaptive weights. The digital-to-analog converter inputs the third digital signal and outputs a fourth analog signal representative of an estimate of a fundamental frequency component of the first analog signal. The analog-to-digital converter inputs a difference between the first and fourth analog signals, and outputs the second digital signal representative of the first analog signal with the fundamental frequency component removed.

Abstract: A decimal floating point (DFP) unit is used to execute fixed point instructions. Two or more operands are accepted, wherein each operand is in a packed binary coded decimal (BCD) format. Any invalid BCD formats are detected by checking the operands for any invalid BCD codes. It is determined if an exception flag exists and, if so, outputting the flag; it is determined if a condition code exists and, if so, outputting the code. An operation is performed on the two or more operands to generate a result; wherein the operation takes place directly on BCD data, thus using the DFP unit to perform a BCD operation; appending a result sign to the result of the operation; and providing the result of the operation and the appended result sign as a result output in a packed BCD format.

Abstract: A technique for operating on points having quantities associated therewith using a table gradient constraint is provided. The technique may include mapping the quantities onto cells, where at least one of the quantities is not on a cell prior to the mapping. The technique may further include applying a table gradient constraint to the mapped quantities, where the applying constrains quantities to maintain variation among the quantities within a bound.