Abstract: An FFT engine implementing a cycle count method of applying twiddle multiplications in multi-stages. When implementing a multistage FFT, the intermediate values need to be multiplied by various twiddle factors. The FFT engine utilizes a minimal number of multipliers to perform the twiddle multiplications in an efficient pipeline. Optimizing a number of complex multipliers based on an FFT radix and a number of values in each row of memory allows the FFT function to be performed using a reasonable amount of area and in a minimal number of cycles. Strategic ordering and grouping of the values allows the FFT operation to be performed in a fewer number of cycles.

Abstract: This is a calculator for tabulating the score in the game of dominos or other tile or card games, wherein the score is determined by symbols or colors rather than numerals, comprising a housing, a display panel, a control panel having a plurality of mathematical function keys and input keys, wherein the input keys have symbols or colors corresponding to the symbols or colors on the game pieces.

Abstract: A modular multiplication method implemented in an electronic digital processing system takes advantage of the case where one of the operands W is known in advance or used multiple times with different second operands V to speed calculation. The operands V and W and the modulus M may be integers or polynomials over a variable X. A possible choice for the type of polynomials can be polynomials of the binary finite field GF(2N). Once operand W is loaded into a data storage location, a value P=?W·Xn+?/M? is pre-computed by the processing system. Then when a second operand V is loaded, the quotient q^ for the product V·W being reduced modulo M is quickly estimated, q^=?V·P/Xn+??, optionally randomized, q?=q^?E, and can be used to obtain the remainder r?=V·W?q?·M, which is congruent to (V·M) mod M. A final reduction can be carried out, and the later steps repeated with other second operands V.

Abstract: A method in a signal processor for filtering samples in a digital signal is provided. An approximate filtered sample is generated as a function of four samples of the digital signal. A correction is generated as a function of the four samples, and a filtered sample is generated by modifying the approximate filtered sample with the correction.

Abstract: An electronic computing circuit for implementing a method for reducing the bit width of two operands from a bit length N to a reduced bit length M, thus, M<N. To enable a wider re-usage of existing designs or building blocks being all specialized to the usual bit length of a power of 2 (8, 16, 32, 64 etc.), the chip structure of which is already highly optimized in regard of speed and space savings, a circuit is implemented as an addend width reduction circuit to perform the steps of: receiving said two N-bit operands as an input, adding the (N?M+1) most significant bits of said two N-bit operands separately in an auxiliary adder logic, calculating at least the two most significant bits of reduced-bit-length output operands in a decision logic processing the add result of said auxiliary adder logic, such that a predetermined post-processing can be correctly performed with said output operands.

Abstract: A division and square root arithmetic unit carries out a division operation of a higher radix and a square root extraction operation of a lower radix. A certain bit number (determined on the basis of a radix of an operation) of data selected from upper bits of the output of a carry save adder and the output of the adder are input to convert the data into twos complement representation data, and the twos complement representation data is shifted a certain bit number (determined on the basis of the radix of the operation) to use the shifted data for a partial remainder of the next digit. Hence, a large number of parts such as registers of a divisor and a partially extracted square root can be commonly used in a divider and a square root extractor to realize an effective and high performance arithmetic unit.

Abstract: A device for implementing a sum-of-products expression includes a first set of 2-input Shift-and-Add (2SAD) blocks receiving a coefficient set/complex sum-of-products expression for generating a first set of partially optimized expression terms by applying recursive optimization therein, a second set of 1-input Shift-and-Add (1SAD) blocks receiving response from the 2SAD blocks for generating a second set of partially optimized expression terms by applying vertical optimization therein, a third set of 2SAD blocks receiving recursively and vertically optimized response from the first set of 2SAD block and the second set of 1SAD blocks for generating a third set of partially optimized expression terms by applying horizontal optimization therein, a fourth set of 2SAD blocks receiving response from the blocks for generating a fourth set of partially optimized expression terms by applying decomposition and factorization, and a fifth set of 2SAD blocks receiving response from the fourth set of 2SAD blocks, for gene

Abstract: First, calculations to solve a given set of simultaneous linear equations are performed using a conjugate gradient method and it is determined, each time the calculations are iterated, whether or not the calculations diverge. If it is determined that the calculations diverge, the initial value of a variable is set to the minimum value and calculations to solve the set of simultaneous linear equations are performed using a conjugate residual method. This allows the set of simultaneous linear equations to be solved even if it is not known whether or not its coefficient matrix is regular.

Abstract: A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic function (LC). In this illustration, the dedicated logic cell comprises two configurable logic functions, two sequential logic functions, a dedicate logic function, and a control logic function. In a first embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-input function, an AND function, an OR function, or an XOR function. In a second embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-to-1 multiplexer function.

Abstract: A CORDIC processor is configured to perform orthogonal or oblique CORDIC projections in order to cancel interference in a received signal. The CORDIC projection can be used to rotate an interference signal vector so that its only non-zero component is in the last Euclidean coordinate of the representative vector. A measurement vector is then subject to the same rotations as the interference vector. As a result of the rotation on the measurement vector, all components of the measurement vector parallel to the interference vector will be resolved onto the same coordinate as the rotated interference vector. The parallel components of the symbol vector can be cancelled by zeroing that coordinate, and the modified measurement vector can then be rotated back to its original coordinates, to produce an orthogonally projected version of the original measurement vector. Typically, the projection is onto a subspace that is orthogonal or oblique to an interference subspace, which may be one-dimensional.

Abstract: In order to output amplitude data with the clock frequency higher than the clock frequency of phase data, the direct digital synthesizer for transmission and detection comprises: a transmitting phase for outputting a first phase data with a first clock frequency; a curtailing unit for outputting a second phase data with a second clock frequency smaller than the first clock frequency, and outputting additional data for compensating for phase information disappeared with curtailing process; an interpolating unit for outputting a third phase data with a third clock frequency larger than the first frequency by implementing interpolating process to the second phase data, and a detecting waveform for outputting amplitude data in accordance with the third phase data. The detecting signal amplitude data can be outputted with the third clock frequency higher than the second clock frequency of the second phase data transmitted.

Abstract: A set of complex rotations are used to implement a unitary “Q” matrix in which each complex rotation is a set of real rotations, where the minimum number of real rotations to perform the complex rotation is three, and where the minimum number of angles to characterize the real rotations is two. The index-angle sets for each successive rotation can be provided by a complex rotor calculation unit, which may be collocated with the complex rotor computational unit, located in a controller such as a DSL optimizer, or located in any other suitable device or apparatus that has performed the QR factorization upon supplied matrix MIMO transfer functions for the vectored channel.

Abstract: A method for determining the correct result and the correct guard and sticky bits to obtain a more accurate result in floating point divide operations is presented. An intermediate divide result or quotient is obtained from a multiply-add hardware pipeline of a floating point processor. Remainders are calculated using the floating point numbers divided, the unit of least precision, and the unit of least precision plus one to determine where the infinitely precise result is with respect to the digital representation of the estimated quotient. Evaluating these remainders and the initial floating point numbers and comparing their signs and magnitudes leads to a selection of one of three choices as the most accurate representation of the infinitely precise result as calculated in the inventive rounding method: the intermediate result minus the unit of least precision; the intermediate divide result; or the intermediate divide result plus the unit of least precision.

Abstract: A minimal area integrated polyphase interpolation filter uses a symmetry of coefficients for a channel of input data. The filter includes an input interface block for synchronizing the input signal to a first internal clock signal; a memory block for providing multiple delayed output signals; a multiplexer input interface block for outputting a selected plurality of signals for generating mirror image coefficient sets in response to a second set of internal control signals, a coefficient block for generating mirror image and/or symmetric coefficient sets, and to output a plurality of filtered signals, an output multiplexer block for performing selection, gain control and data width control on said plurality of filtered signals, an output register block synchronizing the filtered signals, and a control block generating clock signals for realization of the filter and to delay between two channels to access a coefficient set, thereby minimizing hardware in the filter.

Abstract: An image data processing apparatus includes: a data dividing unit dividing arithmetic image data into arithmetic pixel data corresponding to a signal line of a display device; an adder adding first data and second data; and a data delaying unit delaying the added data, wherein the first data is the divided arithmetic pixel data from the data dividing unit, and the second data is the delayed added arithmetic pixel data from the data delaying unit.

Abstract: A source driver for use in a display device having a shift register unit for sequentially activating output signals. The shift register unit includes a plurality of shift registers connected in series, wherein Nth shift register among the plurality of shift registers selects one of an output of a (N?1)th shift register and an output of a (N?A)th shift register according to a channel selection signal to thereby receive the selected signal, where A is a natural number which is greater than or equal to 2.

Abstract: Apparatus and method for providing a dynamic gas-inflated object such as a figure with legs, a torso and head, and a pair of arms. The figure performs generally repetitive movements such as dance-like undulations in a manner that appears to keep time with music. The figure is hollow and connected to a continuous generally constant input flow of air or other gas under pressure. The figure is provided with at least two spaced-apart outlets or vents to allow a continuous discharge of generally all of the air being introduced into the figure. In operation, the figure tends to cycle between extending generally upright, then, as more air is discharged, destabilizing and moving to a contorted or bent position, then, as more air flows in, to extending, etc. The figure may be designed for extensive movement e.g., dancing, or for a narrower range of movements. In a preferred form, the outlets are generally at the top of the head and at the ends of the arms.

Abstract: A candy holding device that is designed to combine candy and which supports the candy. The device includes an upper housing, a middle housing, and a lower housing. The upper housing is a liquid-filled container that has a metallic rotor in the lower portion. The rotor is put in motion by a motor and a magnetic rotor causing a tornado movement within the liquid to provide entertainment. The liquid may also containing objects (glitter, three-dimensional figures, etc.) that are visible to the user. Additionally, at the top of the upper housing is a support for a piece of candy which can be made to be replaceable is desired. The middle housing contains the motor and a switch means. The motor spins the magnetic rotor that in turn spins the metallic rotor in the upper housing. The switch means controls the motor and the lower housing contains the power source.

Abstract: A fishing toy includes a rotary disk and a plurality of toy fishes. The rotary disk has a circular rack, engaging gears installed within the toy fishes. Blocks are installed on the gear. By rotating, the blocks will drive the toy fishes to simulate the action of real fishes. Moreover, the heads of the toy fishes may move upwards and downwards opening and closing the fish mouth. Thus, player may hook a toy fish with a fishing rod.

Abstract: A toy car structure in which a power source such as a motor is activated to drive a gear set for driving decorative car doors, engine hood and car light cover bodies of a car body to open or close so as to create versatile operation.