Abstract: A method and apparatus for estimating the time needed to install software. Configuration information about the data processing system is obtained, as well as information about data needing conversion that is stored on the system. The stand-alone installation time for each portion of the software to be installed is determined and a menu of the installation options is displayed for selection. In response to the selection of options, a determination of whether the installation will be non-linear is made. Non-linear installation involves the ability to install several portions of the software simultaneously, such as in, for example, multiprocessing, multithreading, or parallel processing. In response to a presence of non-linear processing, installation time is determined for the selected options and displayed to the user.

Abstract: New adapter functions for a computer system are moved from existing TTY configuration code to load modules dynamically linked to the TTY configuration code at run time. A load module attribute stored in a vendor-supplied component of a database provides the load module path and name. Third party vendors may then add TTY configuration support by supplying the load module and adding the appropriate attribute(s) to the database, obviating system vendor assistance or source code access. Ease of configuration is enhanced by avoiding displays of TTY device characteristics not supported by currently installed system hardware. An additional type attribute for predefined attributes in the database permits TTY attributes specific to a particular adapter type to be stored under a unique identifier. The additional type attribute and query of a parent device of a TTY for extended attributes for other device types permit third party vendors to add new adapters by generating a load module linked at run time.

Abstract: A file server architecture is disclosed, comprising as separate processors, a network controller unit, a file controller unit and a storage processor unit. These units incorporate their own processors, and operate in parallel with a local Unix host processor. All networks are connected to the network controller unit, which performs all protocol processing up through the NFS layer. The virtual file system is implemented in the file control unit, and the storage processor provides high-speed multiplexed access to an array of mass storage devices. The file controller unit control file information caching through its own local cache buffer, and controls disk data caching through a large system memory which is accessible on a bus by any of the processors.

Abstract: A method and mechanism for automatically correlating a device to its appropriate driver and family within a computer system utilizing candidate matching. A device tree indicating devices coupled to a computer system is available from an operating system. Within the device tree are device nodes which specify a particular device's name (device name) and a property which indicates compatible device names (compatible names) to the particular device. Drivers and corresponding families for devices can be located in RAM, ROM, or in another storage media (such as disk drive). Drivers can include a data field indicating a driver name indicative of a corresponding device with which they operate. For a particular device, the system constructs a candidate list of drivers by comparing (1) the device name and (2) the compatible names from the device tree against all the driver names of data fields of all known drivers.

Abstract: During an initial install process for CD ROM client machines in a computer network, a local client hard drive file system is set up and populated from the CD ROM with client-specific files. Subsequent network-generic and client-specific updates are distributed on CD ROM. Upon subsequent boots from these CD ROMs, the client determines which code on the CD ROM is network-generic and which is client-specific, loading only the latter on the client hard drive(s) and accessing the network-generic code from the CD ROM only.

Abstract: An object synchronization module and corresponding method used in a computer system that includes a plurality of threads of execution and a set of objects that each can only be synchronized with one of the threads at a time. The object synchronization module comprises a cache of synchronization constructs, a free list of un-allocated synchronization constructs, and a cache manager. For each respective thread that seeks synchronization with a respective object, the cache manager allocates a respective synchronization construct in the free list for synchronizing the respective thread with the respective object when none of the synchronization constructs is currently allocated for synchronizing the respective object with any of the threads.

Abstract: The present invention is a novel system and method for supporting the execution of applications of a full service network whereby each application is designed and compiled to execute in a particular execution environment. As the user/subscriber makes a request for a service, the head end accepts the request as one for the downloading of the application associated with the service. The head end downloads the execution environment associated with the particular application. The execution environment is stored in memory at the requesting set-top processor. The application is also downloaded from the head end server to the requesting set-top processor and stored at the set-top processor. The set-top then executes the environment and the application in turn.

Abstract: To perform the modularization and use in a component format of a program and to efficiently create the program. Divide Operations into two, Primitive and Composite Operations, and further classify Composite Operations into Loop, Sequence, and Selection. Then, prepare methods for defining actions common to Operations, methods for defining actions common to Composite Operations, methods for defining actions peculiar to Loop Composite Operations, methods for defining actions peculiar to Sequence Composite Operations, methods for defining actions peculiar to Selection Composite Operations, and methods for defining actions peculiar to Primitive Operations so as to easily and readily create a program with methods for defining actions peculiar individual Operations, a means for inputting data, and a means for making up individual Operations into a tree structure.

Abstract: The present invention teaches a variety of methods, apparatus and data structures for providing data driven patching. According to one embodiment, patches are stored in a known format in a discernible location. In the described embodiment, each fragment code may have a corresponding patch library. This enables the patches to be located and analyzed in a quiescent state. In a method aspect of the present invention, the operating system, or a separate utility program, can evaluate and selectively add patches. Therefore, the present invention introduces a patch integrity validation layer into the patching process. In another method aspect, the invention teaches evaluating the patches in a quiescent state whereby the patches introduced by a program or a combination of programs may be exhaustively evaluated prior to execution.

Abstract: A multiprocessor computer system determines that the hard reset designated BSP has failed by examining its status bits. The designated BSP then selects a processor from among the APs that will take the place of the designated BSP. The selection is accomplished by, successively for every AP indicated to be good by examining its corresponding status flag, determining whether the AP is present, starting up the AP if it is present, determining whether the AP has passed its BIST, and selecting the AP to take the place of the designated BSP if the AP has passed its BIST. The BSP then designates the selected AP as the BSP instead of itself. The bootstrap indicator bit of the selected AP is set to indicate that the AP is the BSP. The bootstrap indicator bit of the designated BSP is cleared. The computer system then undergoes a soft reset which causes the selected AP to become the BSP and begin running the BIOS code from the reset vector.

Abstract: A method and system for allowing an arbitrary operating boot in a shared memory buffer architecture system. A chipset including a memory controller, a bridge, and an arbitration unit is used to control access to a shared physical memory. The physical memory is divided between the system memory and dedicated memory to be used by one or more devices. A portion of the physical memory is allocated as a dedicated memory for some system device. The remainder of the memory may be allocated as system memory. The allocation is performed by a system BIOS either at initial start up or through system BIOS calls made during initialization of the device to use the dedicated memory. Programmable bits in the chipset are programmed to prevent the memory controller from claiming dedicated memory accesses during the boot of an operating system. Since the operating system's attempts to write to the dedicated memory are not claimed by the memory controller during memory sizing, they are forwarded to an I/O bus.

Abstract: An operating system for a computer system having a protection scheme with a plurality of privilege rings provides services for message broadcasting from applications at less privileged rings to virtual drivers at a most privileged ring, and from the virtual drivers to applications. The virtual drivers can perform user mode operations including message broadcasting as an application by synchronizing to a thread of a user mode message server at application time, and setting the thread's user mode context to perform the operations.

Abstract: In a computing system, an in-system programmer includes control logic embedded into the target microprocessor bus address decoder logic, and a memory module in the form of an external device that consists of one or more non-volatile memory chips. With the memory module attached, the microprocessor is led to believe that the in-system programmer is its main memory and the microprocessor turns over control of the computer system to the in-system programmer in an orderly fashion. Program execution comes directly from the in-system memory module. In a stand alone mode the in-system programmer does not require firmware to function. The stand mode is useful in executing temporary firmware without having to alter the target system memory. With embedded programming firmware the in-system programmer is capable of cloning itself in targets that use reprogrammable memory.

Abstract: Aspects of the invention include a method of conducting a reduced length search along a search path. A node which would otherwise occur between a previous and a following node in the search path is eliminated, and information is stored as to whether, had said eliminated node been present, the search would have proceeded to the following node. During the search, a search argument is compared with the stored information, and the search effectively progresses from the previous node directly to the following node if the comparison is positive. In preferred embodiments, some nodes provide result values for the search, and a node is eliminated only if its presence would not affect the result value for the search. In another aspect, the invention features a method of conducting a two mode search of reduced length. For a first mode of the search, nodes along a search path are provided, at least some of the nodes including one or more pointers pointing to other nodes.

Abstract: A human oriented object programming system provides an interactive and dynamic process for debugging computer programs which facilitates the development of complex computer programs such as operating systems and large applications with graphic user interfaces (GUIs). The system performs goal directed debugging in response to a user request. The user merely inputs a high level debugging request, and the system breaks down the request into a set of goals and subgoals for implementing the high level user request. The system automatically develops one or more hypotheses which are tested in attempting to handle the debugging request of the user. Once a hypothesis is found to be true, the system automatically initiates backtracking, and further hypothesis, if necessary, to carry out the user request.

Abstract: A method and apparatus for sharing objects among a group of processes may be accomplished by using a causal time stamp for each conveyance of information between the members of the group of processes. When a process receives an object request from another process, wherein the object request includes identity of the process requesting the objects, a request causal time stamp, and the objects being requested, the receiving process updates its current causal time stamp and grant causal list. The grant causal list includes a prioritized listing of outstanding object requests, where prioritization is based on a predetermined total ordering procedure. Once the grant causal list has been updated, the receiving process determines whether it has one of the needed objects being requested and the request is of a higher priority. If so, the receiving process generates a grant message for the requesting process.

Abstract: OOP environments comprise composite data structures and internal mechanisms for manipulating those structures. The structures are used to allow a user to realize the power of OOP. Hence, the layout of these structures, the way in which the structures inter-relate, and the manner in which they are built and used are all critical to the utility of a particular OOP environment. It is no surprise, then, that manufacturers and suppliers of OOP environments are constantly striving to design composite data structures and internal mechanisms which maximize user productivity. The internal mechanisms and structures that make up the present invention are collectively referred to as the New Object Model (NOM). The composite data structures and organization of the NOM OOP environment provide significant benefits that are not provided by the environments of the prior art.

Abstract: A microprocessor performance monitor and instruction address break point facility are interconnected to provide finer granularity and performance monitoring. The microprocessor is initialized to collect processor statistics preselected prior to performance monitoring. Application start and stop instruction breakpoint addresses are preselected from a software program bounding instructions for which such statistics are desired. An exception handler is installed for instruction address breakpoints (IAB), enabling and disabling the performance monitor and stop addresses, respectively. The IAB register is then initalized to the start address, and the statistics counters are cleared. Upon starting the application, when the application start address instruction is executed, the breakpoint handler obtains control and enables the performance monitor counters, which count the desired statistics after returning from the breakpoint handler. Before returning, the handler sets the IAB register to the stop address.

Abstract: An improved storage mechanism is provided. In a preferred embodiment of the present invention, a container is used for storing objects, links to objects, and other containers. The container of the preferred embodiment is programmable so that the methods of the container are replaceable and the functionality of the container is extendible through the use of a command unit.

Abstract: The invention relates to a telecommunication device having software that is used for controlling function routines, which software includes several separately compilable program units. To reduce the time necessary for manufacturing the telecommunication device and the time necessary for implementing software changes, the program units each have a header which contains addresses (Ap1, Ap2, Ad) used for addressing procedures and/or data combined in the program units. Furthermore, a catalogue is provided which is available to all the loaded program units, which catalogue contains references for addressing the headers of the program units. Within the framework of the manufacture of the telecommunication device, the predefined program units need not be linked when the software of the telecommunication device is implemented.