Patents Examined by Kevin M. Picardai
  • Patent number: 5597736
    Abstract: A semiconductor device with an optically active region which receives light, and has a layer of metal which blocks the light from the substrate. The substrate contains addressing circuitry which can experience current leakage if photocarriers are allowed to form by contact with light. A layer of metal is deposited as an integral part of the device to prevent the light from reaching the substrate.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: January 28, 1997
    Assignee: Texas Instruments Incorporated
    Inventor: Jeffrey B. Sampsell
  • Patent number: 5585310
    Abstract: A semiconductor device includes a semiconductor substrate forming the bottom portion of a package of the device and a ceramic plate forming the upper or lid portion of the device. The substrate includes a layer of metal on its upper surface along the substrate outer edge and spaced apart from electrodes on the substrate upper surface. The ceramic plate includes a copper foil on its lower surface along the outer edge thereof which overlaps and is bonded to the substrate metal layer. The ceramic plate has apertures therethrough which are sealed by copper foils on the inside of the package, the foils being bonded to respective ones of the substrate electrodes. A method of assembly comprises forming an array of integrally connected lids and an army of integrally connected substrates, each of the arrays including the aforementioned layers and foils, bonding the arrays together to form an array of devices, and dicing the bonded together arrays to provide individual devices.
    Type: Grant
    Filed: May 4, 1995
    Date of Patent: December 17, 1996
    Assignee: Harris Corporation
    Inventor: Victor A. K. Temple
  • Patent number: 5472914
    Abstract: A full wafer to full wafer integrated circuit fabrication process wherein substrate removal and replacement of one wafer is used to enable an accurate alignment of this wafer with features of a receiving wafer during a see through alignment step. The invention is disclosed in terms of a wafer of photo field effect transistors being combined with a wafer of circuit devices that attend the photo field effect transistor devices. Use of the invention with the different material combination option desired for a photodetector device and its attending circuitry is also disclosed. Advantages over the more conventional chip by chip combination of wafer devices are also disclosed.
    Type: Grant
    Filed: July 14, 1994
    Date of Patent: December 5, 1995
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: Eric A. Martin, Kenneth Vaccaro, Joseph P. Lorenzo, Andrew Davis
  • Patent number: 5376570
    Abstract: An MOSFET having a nonuniform doping channel and a method for fabricating the same.The MOS transistor having a nonuniform doping channel is comprised of: a gate oxide film formed on a semiconductor substrate provided with a trench; a gate electrode of some size formed on the gate oxide film atop the trench and surroundings, the gate electrode having a portion longer than any other than portion and thus, being asymmetrical with regard to the axis passing the center of the trench; a source region formed in a predetermined portion of the semiconductor substrate neighboring a short portion of the gate electrode; a high density channel region formed by doping impurities having the same type with the semiconductor substrate in a predetermined portion of the semiconductor substrate below a longer portion of the gate electrode; and a drain region formed in a predetermined portion of the semiconductor substrate neighboring the high density channel region.
    Type: Grant
    Filed: December 2, 1993
    Date of Patent: December 27, 1994
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Dae S. Jung, Bong K. Joo, Sang Y. Kim, Han S. Yoon
  • Patent number: 5242862
    Abstract: A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substrate, a second electrode formed on the ground surface and ohmically-contacted with the N-type semiconductor substrate, a semiconductor element formed in the N-type semiconductor substrate and flowing current between the first electrode and the second electrode during ON-state thereof. The device has a reduced ON-resistance thereof.
    Type: Grant
    Filed: February 8, 1991
    Date of Patent: September 7, 1993
    Assignee: Nippondenso Co., Ltd.
    Inventors: Yoshifumi Okabe, Masami Yamaoka, Akira Kuroyanagi
  • Patent number: 5175128
    Abstract: A method for fabricating a semiconductor device comprises the steps of defining a plurality of regions on a substrate, exposing a first pattern that extends over a plurality of such regions such that the first pattern is exposed on the plurality of regions simultaneously, and exposing a plurality of second patterns that are identical in size and shape and isolated from each other, consecutively for each of the plurality of regions.
    Type: Grant
    Filed: November 8, 1991
    Date of Patent: December 29, 1992
    Assignee: Fujitsu Limited
    Inventors: Taiji Ema, Hisatsugu Shirai, Katsuyoshi Kobayashi, Masao Taguchi
  • Patent number: 5134092
    Abstract: A process for forming a deposited film comprises the steps of;(a) disposing in a space for forming a deposited film a substrate having an electron donative surface;(b) introducing to the space for forming a deposited film i) a gas comprising an organic metal compound containing a tungsten atom and ii) a hydrogen gas; and(c) forming a tungsten film on the electron donative surface.
    Type: Grant
    Filed: September 25, 1990
    Date of Patent: July 28, 1992
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shigeyuki Matsumoto, Osamu Ikeda, Kazuaki Ohmi