Abstract: A method for fabricating bond pads on a semiconductor device that reduces intermetallic growth between a metallization layer and a bonding layer is discussed. Initially a metallization layer is deposited over a substrate. Following steps include depositing a barrier layer over the metallization layer, masking a portion of the barrier layer, and etching the barrier layer and the metallization layer. Etching of the barrier and masking layers is performed utilizing the barrier layer mask as a mask for both the barrier layer and the metallization layer. Further steps include depositing a non-conductive layer conformally overlying the barrier layer, masking a portion of the non-conductive layer, and etching the non-conductive layer. Etching the non-conductive layer forms an exposed region of the barrier layer. A later step of this method includes forming a bond layer over the exposed region of the barrier layer, with one possible formation method utilizing an electrolysis process.

Abstract: Disclosed is a method of fabricating a metal semiconductor field effect transistor, comprising the steps for, forming the channel using an ion-implantation, sequentially forming a first insulator layer at a first predetermined temperature and a second insulation layer at second predetermined temperature over the surface of the substrate, etching the first and second insulation layers using a gate pattern of a photo-resist pattern to expose the channel region as a mask, forming a refractory metal over the surface of the first and second insulation layer add the exposed channel region, etching the refractory metal, thereby dividing it into two parts of which one is formed on the channel region and the other is formed on the second insulation layer, selectively etching the first and second insulation layers to lift-off the refractory metal over the first and second insulation layers, thereby forming a gate of a T-shape on the channel region, ion implanting Si into a substrate using the gate and a channel pattern

Abstract: A lead frame design which can be used with a number of different die sizes is described. To customize the lead frame, a punch excises an amount of lead finger material to form a void between the lead fingers for receiving a die. The amount of material removed is greater for larger sized die. A material, such as an adhesive tape, attaches the die to the lead frame. The bond pads on the die are then wire bonded to the lead fingers. The adhesive tape also locks the lead fingers into place, thereby preventing movement which could detach the bond wires from the die or lead frame.

Abstract: A self-aligned bipolar structure for use on SOI (silicon on insulator) substrates is described. This structure does not require etching poly and stopping on single crystal silicon. This is also a process of forming a MOS transistor and a vertical, fully self-aligned bipolar transistor on an insulating substrate.