Abstract: The present disclosure discloses a memory device including a control system for thermal throttling. The control system acquires the temperature of a non-volatile memory element from a temperature detector at a first frequency. Upon determining that the temperature of the non-volatile memory element is above a pre-determined threshold, the control system acquires the temperature of the non-volatile memory element from the temperature detector at a second frequency that is higher than the first frequency and activates the thermal throttling for the non-volatile memory element.

Abstract: An embedded multiprocessor system is provided that includes a multiprocessor system on a chip (SOC), a memory coupled to the multiprocessor SOC, the memory storing application software partitioned into an initial boot stage and at least one additional boot stage, and a secondary boot loader configured to boot load the initial boot stage on at least one processor of the multiprocessor SOC, wherein the initial boot stage begins executing and flow of data from the initial boot stage to the at least one additional boot stage is disabled, wherein the application software is configured to boot load a second boot stage of the at least one additional boot stage on at least one other processor of the multiprocessor SOC and to enable flow of data between the initial boot stage and the second boot stage.

Abstract: In an embodiment, an integrated circuit includes multiple instances of a component (e.g. a processor) and a control circuit. The instances may be configured to operate in various modes. Some of the modes are incapable of presenting a worst-case load on the power supply. The control circuit may be configured to monitor the instances and detect the modes in which the instances are operating. Based on the monitoring, the control circuit may request to recover a portion of the voltage margin established for worst-case conditions in the instances. If the instances are to change modes, they may be configured to request mode change from the control circuit. If the mode change causes an increase in the current supply voltage magnitude (e.g. to restore some of the recovered voltage margin), the control circuit may cause the restore and permit it to complete prior to granting the mode change.

Abstract: A power supplying method for a computer system is proposed. The computer system includes a first computer node, a first power supply unit corresponding to the first computer node, a second computer node, a second power supply unit corresponding to the second computer node, and a connection module electrically connected to the computer nodes and the power supply units. The power supplying method includes: detecting, by the first computer node, whether the second power supply unit operates abnormally; and upon detecting at least that the second power supply unit operates abnormally, controlling, by the first computer node, the first power supply unit to provide electric power to the second computer node through the connection module.

Abstract: An architecture for improving reliability of a multi-server system is provided. The hard disk backplane is provided with at least two hard disk modules, each of which includes a power supply isolation unit and a signal isolation unit. The power connection board is connected to the power supply isolation unit in each of the at least two hard disk modules, so that power supplies of the at least two hard disk module are isolated from each other. Each of the at least two server nodes is connected to at least one of the hard disks through a corresponding signal isolation unit. The server node, the signal isolation unit and the hard disk which are connected to each other form an isolated data communication group. Signal isolation units in any two of isolated data communication groups belong to different hard disk modules.

Abstract: A method from managing power state transitions in a computing system is disclosed. A processor may initiate a change in power state from a first initial power state to a first new power state and, in response to initiating the change, send an initial notification to a system integrated circuit using a first communication channel, and deactivate the first communication based on responses to the initial notification. The processor may enter the first new power state in response to the deactivation of the first communication channel, and send a final notification to a management controller using a second communication channel. The management controller may send a message to the system integrated circuit upon receiving the final notification. The system integrated circuit may then transition from a second initial power state to a second new power state based on the message.

Abstract: A communications system and method provides power-saving while maintaining required protocol timing resolution. In a communication system that requires a high-frequency, high-precision, but high-power, clock source to meet timing requirements, selective disablement and re-enablement of the high-frequency clock provides for both timing precision and power reduction in the system.

Abstract: A semiconductor device includes a voltage sensor which samples a power supply voltage at a speed faster than fluctuations in the power supply voltage and encodes the power supply voltage into a voltage code value. A voltage drop determination circuit detects a voltage drop based on the voltage code value, and a clock control circuit generates a clock. The clock control circuit stops the clock when the voltage drop determination circuit detects the voltage drop. The voltage drop determination circuit includes a prediction computation circuit which looks ahead a voltage value from a history of the voltage code value and predicts a variation value, and the prediction computation circuit includes a circuit for masking a prediction value if a differential value of the prediction value is continuously negative for a predetermined cycle.

Abstract: Disclosed herein are techniques for maintaining a secure execution environment on a server. In one embodiment, the server includes a non-volatile memory storing firmware, a programmable security logic coupled to the non-volatile memory, an adapter device coupled to the programmable security logic, and a processor communicatively coupled to the non-volatile memory via the programmable security logic. The adapter device and/or the programmable security logic can verify the firmware in the non-volatile memory while holding the processor and/or a baseboard management controller (BMC) in power reset, release the processor and the BMC from reset to boot the processor and the BMC after the firmware is verified, and then disable communications between the processor and the BMC and deny at least some requests to write to the non-volatile memory by the processor or the BMC.

Abstract: A frequency calibration method applied to a Universal Serial Bus (USB) device includes: coupling the USB device to a USB host, wherein the USB device comprises at least a programmable oscillator; utilizing the USB device to extract a low frequency periodic signal from the USB host; calibrating the programmable oscillator of the USB device according to the low frequency periodic signal, to make the programmable oscillator generate an oscillating signal having a predetermined frequency; and when the USB device receives the low frequency periodic signal from the USB host, controlling the USB device to generate a predetermined signal having a frequency higher than a frequency of the low frequency periodic signal to the USB host, to make the USB host continuously generate the low frequency periodic signal to the USB device.

Abstract: A microprocessor includes a plurality of processing cores and a configuration register configured to indicate whether each of the plurality of processing cores is enabled or disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a first instance to determine which of the plurality of processing cores is enabled or disabled and generate a respective configuration-related value based on the read of the configuration register in the first instance. The configuration register is updated to indicate that a previously enabled one of the plurality of processing cores is disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a second instance to determine which of the plurality of processing cores is enabled or disabled and generate the respective configuration-related value based on the read of the configuration register in the second instance.

Abstract: An arithmetic processing device includes a plurality of arithmetic processing units each including, an internal circuit that, in an instruction processing state in which an instruction is processed, processes the instruction and that, in an instruction processing stopped state in which instruction processing is stopped, transitions to a state of power save operation, and a power control circuit that disables the power save operation; and a monitoring circuit that monitors the instruction processing stopped state of the plurality of arithmetic processing units and counts the number of the arithmetic processing units in the instruction processing stopped state. The power control circuit of each of the plurality of arithmetic processing units disables the power save operation of the arithmetic processing unit in the instruction processing stopped state, in a case where the number of the arithmetic processing units in the instruction processing stopped state exceeds a threshold.

Abstract: Examples herein disclose a command to control a use of a test key for installation of a test basic input output system (BIOS). The examples validate a command and replace at least a portion of a production BIOS with the test BIOS based on an allowance of the test key.

Abstract: An approach is provided for determining whether to reboot a computing node. Data specifying user behaviors and intra-box and inter-box factors associated with computing nodes are collected and classified in groups. Rules corresponding to the groups are generated. Each rule includes an indicator of whether the corresponding group is associated with permitting or not permitting a reboot. Computing node data is received which specifies intra-box and inter-box factors of the computing node and user operations of the computing node. After determining that the computing node data matches one of the groups, it is determined that a rule corresponding to the group includes an indicator of whether the computing node is permitted to be rebooted. Based on the indicator, the computing node is rebooted or not rebooted.

Abstract: A computer system is securely booted by executing a boot firmware to locate a boot loader and verify the boot loader using a first key that is associated with the boot firmware. Upon verifying the boot loader, computer system executes the boot loader to verify a system software kernel and a secure boot verifier using a second key that is associated with the boot loader. The secure boot verifier is then executed to verify the remaining executable software modules to be loaded during boot using a third key that is associated with the secure boot verifier. During boot, state data files of the computer system are mounted in a namespace that is isolated from the namespaces in which the executable software modules are mounted.

Abstract: A communications system and method provide power-saving while maintaining required protocol timing resolution. In a communication system that requires a high-frequency, high-precision, but high-power, clock source to meet timing requirements, selective disablement and re-enablement of the high-frequency clock provides for both timing precision and power reduction in the system.

Abstract: A computer system is rebooted upon crash without running platform firmware and without retrieving all of the modules included in a boot image from an external source and reloading them into system memory. The reboot process includes the steps of stopping and resetting all of the processing units, except one of the processing units that detected the crash event, selecting the one processing unit to execute a reboot operation, and executing the reboot operation to reboot the computer system.

Abstract: An input/output (I/O) interface-based signal output method and apparatus. The method includes determining whether a voltage output by a core power supply domain of a first chip is lower than a preset threshold voltage of the first chip, and when the voltage output by the core power supply domain is lower than the threshold voltage, generating a first level signal according to a control function of the first chip over a second chip, where the first level signal is used to enable the second chip to be in an ignoring state after the second chip receives the first level signal, and sending the first level signal to the second chip through an I/O interface, where the ignoring state indicates that the second chip ignores a control signal and a data signal that are sent by the first chip where the method improves stable performance of a chip product.

Abstract: For power management in a computing system, component utilization is dynamically managed within the computing system according to a calculated aggregate energy consumed by each one of a set of processors. Each of a plurality of energy factors are measured individually between each one of the set of processors to accumulate the calculated aggregate energy in real time.

Abstract: In one embodiment, a processor comprises: a first domain including a plurality of cores; a second domain including at least one graphics engine; and a power controller including a first logic to receive a first performance request from a driver of the second domain and to determine a maximum operating frequency for the first domain responsive to the first performance request. Other embodiments are described and claimed.