Abstract: A multi-processor arrangement having an interprocessor communication path between each of every possible pair of processors, in addition to I/O paths to and from the arrangement, having signal processing functions configurably embedded in series with the communication paths and/or the I/O paths. Each processor is provided with a local memory which can be accessed by the local processor as well as by the other processors via the communications paths. This allows for efficient data movement from one processor's local memory to another processor's local memory, such as commonly done during signal processing corner turning operations. The configurable signal processing logic may be configured to host one or more signal processing functions to allow data to be processed prior to its deposit into local memory.

Abstract: A programmable unit includes a command execution unit for carrying out commands, a memory device for storing data required for command execution and data emitted from the command execution unit, and a buffer-storage device for buffer storing the data emitted from the command execution unit. The command execution unit writes to the buffer-storage device data to be transferred to the memory device. The data written to the buffer storage device is transferred to the memory device at a later time. The programmable unit is distinguished by forming the buffer-storage device as a stack, and/or by providing a control apparatus that, when required, causes data stored in the buffer-storage device to be moved temporarily to another memory device. Such a programmable unit can carry out any buffer storage of events that may possibly be required quickly and easily in all circumstances.

Abstract: A system, circuit, and method are presented for adjusting a prefetch rate of a prefetch unit from a first rate to a second rate by determining a probability factor associated with a branch instruction. The circuit and method may determine the probability factor based on a type of disparity associated with the branch instruction. The circuit and method may further be adapted to calculate the second rate based on the probability factor. The ability to adjust the prefetch rate of a prefetch unit advantageously decreases the number of memory transactions, thereby decreasing the power consumption of a processing unit.

Abstract: The present invention provides an apparatus and method for storing instruction set information. The apparatus comprises a processing circuit for executing processing instructions from any of a plurality of instruction sets of processing instructions, each processing instruction being specified by an instruction address identifying that processing instruction's location in memory. A different number of instruction address bits need to be specified in the instruction address for processing instructions in different instruction sets. The apparatus further comprises encoding logic for encoding an instruction address with an indication of the instruction set corresponding to that instruction to generate an n-bit encoded instruction address.

Abstract: A method and system for recovering a global history vector. In the event of a non-branch flush, a tag may be received by a queue configured to store information about branch instructions. The queue may read a copy of the global history vector from an entry indexed by the tag. This copy may be inserted in a global history vector mechanism (“GHV mechanism”) configured to manage the global history vector. If the flush operation is a flush to a group of instructions that contains no branch instructions and the tag does not equal the next-to-write pointer in the queue, then the queue may transmit a command to the GHV mechanism to enter a mode where the GHV mechanism does not update the global history vector until the next branch instruction is fetched.

Abstract: A method for controlling functional units in a processor, according to which in a configuration a sequence of primary instruction words which consists of several instruction word parts and originates from a translation of a program code is compressed and stored as a sequence of associated program words. The invention also relates to a processor system for carrying out this method. The aim of the invention is to increase operating speed in an application-specific manner while retaining a low program word width. To this end, as regards the method, a program word contains a first characteristic of a primary instruction word and instruction word parts which differentiate the primary instruction word belonging to the program word from the primary instruction word belonging to the characteristic.

Abstract: A processor is described in which the need to encode no-operation instructions (nops) in the program is minimised by providing a device for generating nops in response to information encoded in operative instructions.

Abstract: A register window fill technique for a retirement window having an entry size less than a number of fill instructions used in a fill condition is provided. The technique uses modified fill instructions that allow the retirement window to retire a portion of the fill instructions without having to determine whether a remaining portion of the fill instructions will execute without exceptions.

Abstract: A register window spill technique for an retirement window having an entry size less than a number of spill instructions used in a spill condition is provided. The technique uses modified spill instructions that allow the retirement window to retire a portion of the spill instructions without having to determine whether a remaining portion of the spill instructions will execute without exceptions.

Abstract: Multiple register input multiplexors select a respective one of the results generated by operation units, and store the selected results in respective architecture registers as specified by the corresponding instructions (from which the results are generated). A forwarding multiplexor receives the results before the results are provided to the register input multiplexors, and selects one of the results for use as an operand for execution of a dependent instruction. As the forwarding multiplexor receives the results at a point before the inputs of the register input multiplexors, the time duration required to forward the results may be minimized, and a greater instruction throughput performance may be attained in a processor.