Abstract: Methods and apparatus for heat-treating a workpiece are disclosed. An illustrative method includes measuring deformation of a workpiece during heat-treating thereof, and taking an action in relation to the heat-treating of the workpiece, in response to the measuring of the deformation of the workpiece. The workpiece may include a semiconductor wafer. Taking an action may include applying a deformation correction to a temperature or reflectivity measurement of the wafer during thermal processing, or may include modifying the heat-treating of the wafer, for example.

Abstract: A method of manufacturing a device includes providing a semiconductor chip having a first face and a second face opposite to the first face with a contact pad arranged on the first face. The semiconductor chip is placed on a carrier with the first face facing the carrier. The semiconductor chip is encapsulated with an encapsulation material. The carrier is removed and the semiconductor material is removed from the second face of the first semiconductor chip without removing encapsulation material at the same time.

Abstract: A semiconductor device includes a semiconductor substrate including a first region and a second region, a first high-k dielectric film pattern on the first region, a second high-k dielectric film pattern on the second region and having the same thickness as the first high-k dielectric film pattern. First and second work function control film patterns are positioned on the high-k dielectric film patterns of the first region. Third and fourth work function control patterns are positioned on the high-k dielectric film pattern of the second region, the first work function control pattern being thicker than the third work function control pattern and the fourth work function control pattern being thicker than the second.

Abstract: The oxide semiconductor film has the top and bottom surface portions each provided with a metal oxide film containing a constituent similar to that of the oxide semiconductor film. An insulating film containing a different constituent from the metal oxide film and the oxide semiconductor film is further formed in contact with a surface of the metal oxide film, which is opposite to the surface in contact with the oxide semiconductor film. The oxide semiconductor film used for the active layer of the transistor is an oxide semiconductor film highly purified to be electrically i-type (intrinsic) by removing impurities such as hydrogen, moisture, a hydroxyl group, and hydride from the oxide semiconductor and supplying oxygen which is a major constituent of the oxide semiconductor and is simultaneously reduced in a step of removing impurities.

Abstract: A semiconductor device comprises a first substrate portion and a second substrate portion disposed a distance away from the first substrate portion. The first substrate portion includes a first active semiconductor layer defining at least one semiconductor fin and a first polycrystalline layer formed directly on the fin. The first polycrystalline layer is patterned to define at least one semiconductor gate. The second substrate portion includes a doped region interposed between a second active semiconductor region and an oxide layer. The oxide layer protects the second active semiconductor region and the doped region. The doped region includes a first doped area and a second doped area separated by the first doped region to define a depletion region.

Abstract: A planar semiconductor device including a semiconductor on insulator (SOI) substrate with source and drain portions having a thickness of less than 10 nm that are separated by a multi-layered strained channel. The multi-layer strained channel of the SOI layer includes a first layer with a first lattice dimension that is present on the buried dielectric layer of the SOI substrate, and a second layer of a second lattice dimension that is in direct contact with the first layer of the multi-layer strained channel portion. A functional gate structure is present on the multi-layer strained channel portion of the SOI substrate. The semiconductor device having the multi-layered channel may also be a finFET semiconductor device.

Abstract: A semiconductor device having a solid-state image sensor which can prevent inter-pixel crosstalk more reliably. The device includes: a semiconductor substrate having a main surface; a first conductivity type impurity layer located over the main surface of the substrate; a photoelectric transducer including a first conductivity type impurity region and a second conductivity type impurity region which are joined to each other over the first conductivity type impurity layer; and transistors which configure a unit pixel including the photoelectric transducer and are electrically coupled to the photoelectric transducer. At least part of the area around the photoelectric transducer in a plan view contains an air gap and also has an isolation insulating layer for electrically insulating the photoelectric transducer and a photoelectric transducer adjacent to it from each other. The isolation insulating layer abuts on the top surface of the first conductivity type impurity layer.

Abstract: Narrow-body FETs, such as, FinFETs and trigates, exhibit superior short-channel characteristics compared to thick-body devices, such as planar bulk Si FETs and planar partially-depleted SOI (PDSOI) FETs. A common problem, however, with narrow-body devices is high series resistance that often negates the short-channel benefits. The high series resistance is due to either dopant pile-up at the SOI/BOX interface or dopant diffusion into the BOX. This disclosure describes a novel narrow-body device geometry that is expected to overcome the high series resistance problem.

Abstract: Disclosed are methods for forming a metal-containing layer on a substrate. The methods include providing a vapor and at least one reaction gas and reacting the vapor and the reaction gas with the substrate by a deposition process. The vapor may be selected from the group consisting of (Cp)V(?NtBu)(NEt2)2; (Cp)V(?NtBu)(NMe2)2; (Cp)V(?NtBu)(NEtMe)2; (Cp)V(?NiPr)(NEt2)2; (Cp)V(?NiPr)(NMe2)2; (Cp)V(?NiPr)(NEtMe)2; (Cp)V(?NC5H11)(NEt2)2; (Cp)V(?NC5H11)(NMe2)2; (Cp)V(?NC5H11)(NEtMe)2; (Cp)Nb(?NtBu)(NEt2)2; (Cp)Nb(?NtBu)(NMe2)2; (Cp)Nb(?NtBu)(NEtMe)2; (Cp)Nb(?NiPr)(NEt2)2; (Cp)Nb(?NiPr)(NMe2)2; (Cp)Nb(?NiPr)(NEtMe)2; (Cp)Nb(?NC5H11)(NEt2)2; (Cp)Nb(?NC5H11)(NMe2)2; and (Cp)Nb(?NC5H11)(NEtMe)2.

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate, and a gate insulator arranged on the semiconductor substrate. The device further includes a gate electrode including a semiconductor layer and a metal layer which are sequentially arranged on the gate insulator. The device further includes a contact plug arranged on the gate electrode to penetrate the metal layer, and having a bottom surface at a level lower than an upper surface of the semiconductor layer.

Abstract: A light emitting diode includes a substrate, a first semiconductor layer, a luminous layer, a second semiconductor layer, a current diffusion layer, a third semiconductor layer, a first electrode, a second electrode, and an insulation layer. The first semiconductor layer is formed above the substrate. The luminous layer is formed on the first semiconductor layer, and exposes a portion of the first semiconductor layer. The second semiconductor layer is formed on the luminous layer. The current diffusion layer is formed on the second semiconductor layer. The third semiconductor layer is formed on the current diffusion layer. The first electrode is formed on the first semiconductor layer. The second electrode includes a base portion formed on the surface of the substrate, and plural comb structures extending upward vertically. Each tip of the comb structure is in the third semiconductor layer. The insulation layer exposes the tip of each comb structure.

Abstract: A solid-state image pickup device includes a semiconductor substrate in which photoelectric conversion units are arranged. An insulator is disposed on the semiconductor substrate. The insulator has holes associated with the respective photoelectric conversion units. Members are arranged in the respective holes. A light-shielding member is disposed on the opposite side of one of the members from the semiconductor substrate, such that only the associated photoelectric conversion unit is shielded from light. In the solid-state image pickup device, the holes are simultaneously formed and the members are simultaneously formed.

Abstract: Methods for fabricating silicon nanowire chemical sensing devices, devices thus obtained, and methods for utilizing devices for sensing and measuring chemical concentration of selected species in a fluid are described. Devices may comprise a metal-oxide-semiconductor field-effect transistor (MOSFET) structure.

Abstract: In one embodiment a method of forming a compressive polycrystalline semiconductive material layer is disclosed. The method comprises forming a polycrystalline semiconductive seed layer over a substrate and forming a silicon layer by depositing silicon directly on the polycrystalline silicon seed layer under amorphous process conditions at a temperature below 600 C.

Abstract: A method of fabricating a semiconductor substrate, includes forming a first semiconductor layer on a substrate, forming a metallic material layer on the first semiconductor layer, forming a second semiconductor layer on the first semiconductor layer and the metallic material layer, etching the substrate using a solution to remove the metallic material layer and a portion of the first semiconductor layer, and forming a cavity in the first semiconductor layer under where the metallic material layer was removed.

Abstract: A nonvolatile memory element which inhibits deterioration of an oxygen concentration profile of a variable resistance layer due to a thermal budget and is able to stably operate at low voltages, and a method for manufacturing the nonvolatile memory element are provided. The nonvolatile memory element includes a first electrode layer formed above a substrate, a variable resistance layer disposed on the first electrode layer, and a second electrode layer disposed on the variable resistance layer, and the variable resistance layer has a two-layer structure in which an oxygen- and/or nitrogen-deficient tantalum oxynitride layer and a tantalum oxide layer are stacked.

Abstract: A device and method for fabricating a nanowire include patterning a first set of structures on a substrate. A dummy structure is formed over portions of the substrate and the first set of structures. Exposed portions of the substrate are etched to provide an unetched raised portion. First spacers are formed about a periphery of the dummy structure and the unetched raised portion. The substrate is etched to form controlled undercut etched portions around a portion of the substrate below the dummy structure. Second spacers are formed in the controlled undercut etched portions. Source/drain regions are formed with interlayer dielectric regions formed thereon. The dummy structure is removed. The substrate is etched to release the first set of structures. Gate structures are formed including a top gate formed above the first set of structures and a bottom gate formed below the first set of structures to provide a nanowire.

Abstract: A low capacitance transient voltage suppressor with reduced clamping voltage includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A first trench is at an edge of the buried layer and an edge of the implant layer. A second trench is at another edge of the buried layer and extends into the implant layer. Each trench is lined with a dielectric layer. A set of source regions is formed within a top surface of the second epitaxial layer. The trenches and source regions alternate. A pair of implant regions is formed in the second epitaxial layer.

Abstract: A finned structure is fabricated using a bulk silicon substrate having a carbon doped epitaxial silicon layer. A pFET region of the structure includes silicon germanium fins. Such fins are formed by annealing the structure to mix a germanium containing layer with an adjoining crystalline silicon layer. The structure further includes an nFET region including silicon fins formed from the crystalline silicon layer. The germanium containing layer in the nFET region is removed to create a space beneath the crystalline silicon layer in the nFET region. An insulating material is provided within the space. The pFET and nFET regions are electrically isolated by a shallow trench isolation region.

Abstract: A method for developing a custom device, the method including: programming a programmable device, where the programmable device includes a layer of monocrystalline first transistors and alignment marks, the first layer of monocrystalline first transistors is overlaid by interconnection layers, the interconnection layers are overlaid by a second layer of monocrystalline second transistors, where the interconnection layers include copper or aluminum, where the programming includes use of the second transistors, where the programming includes use of N type transistors and P type transistors, and where the programmable device includes at least one programmable connection; and then a step of producing a volume device according to a specific programmed design of the programmable device, where the volume device includes the at least one programmable connection replaced with a lithography defined connection, and where the volume device does not have the second layer.