Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.
Type:
Grant
Filed:
August 22, 2003
Date of Patent:
May 20, 2008
Assignee:
AmberWave Systems Corporation
Inventors:
Richard Westhoff, Vicky Yang, Matthew Currie, Christopher Vineis, Christopher Leitz