Abstract: The present invention provides a method and mechanism for simulating complex digital circuits using hybrid control and data flow representations. Specifically, the invention provides a method of controlling the simulation of a digital circuit in such a way that desired functions are annotated for subsequent analysis. A hardware design code describing the digital circuit is converted to an assignment decision diagram (ADD) representation that is then annotated with one or more control nodes that are used for maintaining control flow through a simulator. In this way, one or more break points are created that allow the simulator to stop at associated points in the simulation.

Abstract: A co-simulation design system that runs on a host computer system is described that includes a hardware simulator and a processor simulator coupled via an interface mechanism. The execution of a user program on a target processor that includes a cache is simulated by executing an analyzed version of the user program on the host computer system. The analysis adds timing information to the user program so that the processor simulator provides accurate timing information whenever the processor simulator interacts with the hardware simulator. The analysis also adds hooks to the user program such that executing the analyzed user program on the host computer system invokes a cache simulator that simulates operation of the cache.

Abstract: A spray coating simulation for a robotic spray gun assembly imports a discretized model of an object geometry. Next, the simulator imports a numerically characterized spray pattern file and a robot motion file having a plurality of motion positions, dwell times and orientations defining a motion path of the spray gun. The individual motion positions within the motion file are read and a determination is made as to which portions of the object geometry are visible at each motion position. Next, a coating thickness at each visible portion of the object geometry is computed, based on the specified spray pattern data, the dwell time and the orientation of the robot motion path, for each motion position. Finally, the total coating thickness over the object geometry is calculated.

Abstract: A processor performance evaluation system and method provides a method of model decomposition and trace attribution by first decomposing a full pipelined model of the entire system into a main model and one or more additional sub-models, such that it is possible to build fast trace-driven non-pipelined simulation models for the sub-models to compute specific metrics or values, which would be required during full-model, pipeline simulation. The main model is a fully pipelined model of the entire system; however, the simulation work required for the sub-units characterized by the sub-models is not coded into the simulation engine. Instead, the necessary values are provided from encoded fields within the input trace.

Abstract: A computer system, computer program product, and method for solving a combinational logic verification problem with respect to two combinational circuits includes Boolean SAT checking integrated with binary decision diagrams (BDD) use. A fanout partition of a miter circuit formed from the two combinational circuits is reduced to BDD form, while the fanin partition is represented by SAT clauses. As SAT solutions are evaluated, variables in the cutset between the fanout and fanin partitions are assigned values. In a preferred embodiment, each assignment to a cutset variable is checked against an onset of the BDD prior to continuing with SAT solution seeking.

Abstract: A method and system of providing an interactive user interface for a user to specify one or more familial relationships between regions includes inputting, by the user, a network model including one or relationships within at least one of the regions and/or across at least two of the regions. The user defines at least one multiplicity relationship for the network model, including one or more familial relationships within the regions and/or across the regions using one or more familial indices. The computer simulates the network model, and outputs simulation results responsive thereto.

Abstract: Methods and computer programs for logic circuit design minimization with Identity cell representation is provided which can simplify logic circuit design by combining and minimizing Identity cells and thereby reducing the number of gates in the logic circuit. All possible Identity cells from a given logic function are generated by combining every possible pair of logic terms, then equivalent Identity cell terms are eliminated and the best subset of Identity cell terms which covers all the minterms of the given logic function is provided.The I-cell term representation is sufficiently broad in its scope to allow representation of sub-functions such as ABC+ABC as a single entity that can be readily used for minimization which may be advantageously used in logic circuit fabrication and design.

Abstract: The present disclosure provides a method and apparatus for using frequency domain data, such as S-parameters, in a time-based simulator. S-parameters are either input to the simulator, or are empirically measured, at selected frequencies. Preferably, the selected frequencies are related to one another by a logarithmic scale, providing for determination of a system transfer function which is accurate across a very wide range of frequencies, from near zero hertz, to frequencies on the order of a hundred gigahertz. The transfer function preferably takes the form of a fitted polynomial, obtained using FDSI techniques. In addition, recursive convolution may be employed to operate in the time domain on inverse Laplace Transforms of the fitted transfer function and time-domain simulator test signals.

Abstract: In designing a logic network a plurality of nodes are identified which define incompatible output phase assignments. Certain of the incompatible nodes are selected for assigning the output phases, so that NOT gates in the fan-out cone of such a selected node are moved to the network outputs. In a further aspect, the selecting is in response to the number of logic gates in the fan-in cones of the incompatible nodes.

Abstract: A computer-based system and method automate the generation of megacells in the design and layout of integrated circuits. The preferred method utilizes an automatic design generator having a user interface which receives design requirements for a megacell or other complex integrated circuit design. A megacell processor receives the design requirements for the megacell and retrieves relevant megacell implementations from a megacell library. Stored megacell benchmarks are then retrieved from a megacell benchmark memory and applied to corresponding megacells to determine which of the various implementations optimally satisfies the user design requirements. Once the optimal megacell implementation is selected, the megacell processor produces a logic design consisting of a net list and a physical design consisting of design directives which are then used to place and route the megacell as a finished layout.

Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arrangement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.

Abstract: A vehicle speed calculation system capable of calculating a reference vehicle speed of a fourwheel drive vehicle with high accuracy when a fourwheel slip or lock occurs. An integrated value of a longitudinal acceleration is forcedly used for the calculation of the reference vehicle speed when the vehicle is accelerated and a variation of a lowest wheel speed is negative or when the vehicle is decelerated and a variation of a highest wheel speed is positive.

Abstract: A method and system are provided for positioning a gasoline engine throttle in response to an angular position input command signal. A multi-phase variable reluctance motor positions the throttle in response to motor current commands from a micro-controller. The micro-controller receives and processes the position input command and throttle position feedback signals from a multi-phase variable inductance position encoder rotatably coupled with the motor shaft. The motor current command are obtained from look-up tables that are derived from empirical data of the motor. The motor current command tables are a mapping from motor rotor position and desired motor torque to desired motor currents in the appropriate phases of the motor to hold the load.

Abstract: An engine monitor includes, in a self-contained preferably sealed unit, a spark sensor, inductively and capacitively coupled through the case to a spark pick up wire, a timer, and a running time detector, responsive to inputs from the spark pick up to provide total running time, job time, and service time metering. Preferably, storage means are included for storing maximum RPM and spark mode data, that is, data indicating the number of firings per RPM for the particular engine, as well as a preset service interval and one or more auxiliary timers.

Abstract: A process for steering a road vehicle having all wheel steering for placing the vehicle into, within, and out of constricted spaces and small, constricted travel areas, the vehicle having a front, a rear, a longitudinal axis, front wheels steerable rear wheels, the all wheel steering being proportional between the front and rear wheels for turning the vehicle about a turning radius, apparatus for determining the distance of the vehicle from an obstacle, and apparatus for restricting or disabling the steerability of the rear wheels in response to the proximity of the obstacle, by driving the vehicle to the proximity of the obstacle, determining the distance of the vehicle from a location on the obstacle when the vehicle approaches the obstacle closer than by a predetermined distance, determining the relative angle of the longitudinal axis to the location on the obstacle, and adjusting the steering of the rear wheels in response to changes in the angular position to move the vehicle along the obstacle without t

Abstract: An emulation system for emulating an application specific integrated circuit (ASIC) type microcomputer including a central processing unit, a user specific peripheral function unit and a user specific logic circuit, which are integrated together on a single chip. The emulation system includes a first integrated circuit for emulating the central processing unit, and second and third integrated circuits each of which comprises the ASIC-type microcomputer. Each of the second and third integrated circuits can selectively operate in a first evaluation chip mode in which the central processing unit and the user specific logic circuit are isolated from an internal bus, and in a second evaluation chip mode in which the central processing unit and the user specific peripheral function unit are isolated from the internal bus. The first integrated circuit is connected through an peripheral bus to the internal bus of each of the second and third integrated circuits.

Abstract: A method and apparatus for managing color data in a predetermined color space by using a pallet converting mechanism, in which a pallet management table can be efficiently registered and updated. An entry number accessing a table entry in the pallet management table is formed by combining the components of the color data. Table data, obtained by combining remaining components of the color data which are not used for the formation of the entry number, is stored into the table entry identified by the entry number. There is also the conversion of color data to pallet data, which corresponds to entry numbers, and the reverse conversion to reconstruct the original color data from pallet data and entry number information. Validity information indicative of the validity of the table entry is also registered into the table entry of the pallet management table, so that an available table entry at the time of new registration can be immediately found out.

Abstract: For laying out power supply wiring conductors in integrated circuits, a plurality of function blocks are located, and laid-out positions of power supply wiring conductors of first and second levels are determined on the basis of the located function blocks. Power supply wiring conductors are temporarily laid out by using power supply wiring conductors of third and fourth levels, so as to connect the temporarily laid third and fourth level power supply wiring conductors to the power supply wiring conductors of the first and second levels, so that a power supply network composed of all the power supply wiring conductors is constructed in a desired chip area.

Abstract: The position of the operator's finger or an actuating device on a transducing surface is used for controlling the level of utilization devices including theater lights controlled by an automated theater light control system. The transducing surface, which may be either an analog or a digital device, is elongated in shape and is immediately adjacent to an elongated display having individual light emitting devices to indicate the level of the utilization device being controlled. Circuitry connected to the transducing surface produces a first signal to indicate when an operator's finger or an actuating device is present on the transducing surface, and it produces a second signal to indicate the position of the operator's finger or the actuating device on the transducing surface. The second signal is supplied to the display, and the first and second signals are supplied to the utilization device.

Abstract: This invention refers to a .[.plant operating.]. method .Iadd.and apparatus for guidance of an operation .Iaddend.for overcoming an abnormal status of a plant. A plant data is detected from the plant, and all plant state members indicating an abnormality of the plant are identified from the plant data. The plant operating method .Iadd.and apparatus .Iaddend.includes .Iadd.apparatus for .Iaddend.