Patents Examined by Khahn Duong
  • Patent number: 6875663
    Abstract: The present invention provides a method of fabricating a semiconductor device in which deterioration in a transistor characteristic is prevented by preventing a channel stop implantation layer from being formed in an active region. A resist mask is formed so as to have an opening over a region in which a PMOS transistor is formed. Channel stop implantation is performed with energy by which ions pass through a partial isolation oxide film and a peak of an impurity profile is generated in an SOI layer, thereby forming a channel stop layer in the SOI layer under the partial isolation oxide film, that is, an isolation region. An impurity to be implanted here is an N-type impurity. In the case of using phosphorus, its implantation energy is set to, for example, 60 to 120 keV, and the density of the channel stop layer is set to 1×1017 to 1×1019/cm3. At this time, the impurity of channel stop implantation is not stopped in the SOI layer corresponding to the active region.
    Type: Grant
    Filed: September 9, 2002
    Date of Patent: April 5, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Toshiaki Iwamatsu, Takashi Ipposhi, Takuji Matsumoto, Shigenobu Maeda