Abstract: A word-line enable pulse generator for a SRAM is provided. The word-line enable pulse generator includes a delay unit. The delay unit is configured to delay a word-line enable pulse signal to be provided to a plurality of word line drivers of the SRAM. The delay unit includes a first transistor coupled between the plurality of word line drivers of the SRAM and a first power source, a resistance unit coupled between the first transistor and a second power source that is different from the first power source, and a second transistor coupled between the first transistor and the resistance unit. The first transistor has a gate for receiving an enable signal. The second transistor has a gate for receiving the enable signal. An edge of the word-line enable pulse signal is delayed from the enable signal by a delay time corresponding to a resistance of the resistance unit.

Abstract: A control system may include a fault detection system, an electromechanical actuator, the electromechanical actuator electronically coupled to the fault detection system, and a failure simulation apparatus mechanically coupled between the electromechanical actuator and a load, the failure simulation apparatus selectively applies an external resistive force to the electromechanical actuator.

Abstract: Described is a write scheduling scheme for a SSD that significantly increases read performance, in certain embodiments by about 50% compared to a conventional standard write scheduling schemes, for mixed read-write workloads while maintaining the write bandwidth.

Abstract: According to one embodiment, a magnetic memory device includes a memory cell array unit including magnetoresistive elements provided in an array in first and second directions, each including a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction, and a nonmagnetic layer between the first and second magnetic layers, first transistors provided in an array in the first and second directions, and electrically connected to the magnetoresistive elements, respectively, switching units each electrically connected to corresponding ones of the first transistors in series, and each including at least one second transistor, wherein the first magnetic layers are separated from each other in the first and second directions, and the second magnetic layers are continuously provided in the first and second directions.

Abstract: Embodiments include a sense amplifier circuit including first and second paths that may be selectively coupled to a memory cell or a reference cell as part of a two-phase read process. The sense amplifier may include a biasing circuit to provide an adaptive bias voltage to a transistor of the first and/or second path to cause the transistor to provide a voltage across the memory cell and/or reference cell that is substantially constant across process corners. Additionally, or alternatively, the sense amplifier may include a DC-coupled regenerative latch circuit to generate a digital output signal based on a voltage difference between nodes of the first and second paths at or near the end of the second phase. Additionally, or alternatively, trimmable offset resistors may adjust a resistance value provided to the sense amplifier by the memory cell and/or reference cells. Other embodiments may be described and claimed.

Abstract: A memory controller may be provided. The memory controller may include a wear-leveler may be configured to determine whether execution of a swapping operation is required based on reception of a write command for a stack region.

Abstract: Provided are a battery state estimation method and system and a recording medium for performing the method. The battery state estimation is provided by applying an ARX model and a dual extended Kalman filter. A battery state estimation system estimates a parameter of a battery model using an ARX model and estimates a battery state by applying the estimated parameter of the battery model to a dual extended Kalman filter including a state filter used to estimate a state of charge (SOC) and a weight filter used to estimate a state of health (SOH) of the battery.

Abstract: A data latch circuit includes a first inverter circuit having a first input terminal and a first output terminal, and connected between a first voltage source and a second voltage source, a second inverter circuit having a second input terminal electrically connected to the first output terminal and a second output terminal electrically connected to the first input terminal, and connected between the first voltage source and the second voltage source, a first transistor electrically connected between the first voltage source and the first inverter circuit, a second transistor electrically connected between the second voltage source and the first inverter circuit, a first switch circuit that controls an electrical connection between the first output terminal and a first bus, and a second switch circuit that controls an electrical connection between the first output terminal and a second bus.

Abstract: A method of reading data from a first memory device includes generating a first read command based on a first request which requests to generate the first read command for first data stored in a first address region of the first memory device, generating a second read command for second data stored in a second address region of the first memory device, generating a third read command based on a second request which requests to generate the third read command for third data stored in a third address region of the first memory device, executing the first read command and the third read command to read the first data and the third data, respectively, from the first memory device, and after the executing the first read command and the third read command, executing the second read command to read the second data from the first memory device.

Abstract: A semiconductor device may be provided. The semiconductor device may be configured for detecting a defect of a fuse set. The semiconductor device may include a pseudo initial signal generator configured to generate pseudo initial information on the basis of a test mode signal. The semiconductor device may include a fuse-set defect detector configured to compare fuse-set information of a fuse set or the pseudo initial information with a reference value on the basis of a fuse-set address, and detect a defect of the fuse set.

Abstract: Examples disclosed herein relate to a circuit having first and second analog processors and an analog-to-digital converter coupled to the first and second analog processors. The first analog processor provides a first analog signal having a voltage representing a function of a first vector and a second vector. The second analog processor provides a second analog signal having a voltage representing a function of a binary inverse of the first vector and the second vector. The analog-to-digital converter receives the first analog signal and the second analog signal, compares a signal selected from a group consisting of the first analog signal and the second analog signal to a reference voltage and based on the comparison to the reference voltage, determines a digital result representing the function of the first vector and the second vector.

Abstract: Memory devices and methods of operating memory devices are shown. Configurations described include a memory cell string having an elongated n type body region and having select gates with p type bodies. Configurations and methods shown can provide a reliable bias to a body region for memory operations such as erasing.

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Prior to writing a logic value to a ferroelectric memory cell, a digit line of a ferroelectric memory cell may be biased to a first voltage, and a cell plate of the ferroelectric memory cell may be biased to a second voltage. A magnitude of a difference between the first voltage and the second voltage may be greater than a magnitude of a write voltage for the first ferroelectric memory cell. The magnitude of the difference between the first voltage and the second voltage may decrease the time to reach a write voltage for the ferroelectric memory cell. Several example cell plate drivers are also disclosed.

Abstract: A discharge circuit includes first and second transistors of a first polarity, third and fourth transistors of a second polarity, and first and second current sources having first ends electrically connected to first end of the third transistor and first end of the fourth transistor, respectively, and second ends supplied with a first voltage. First end of the first transistor is supplied with a second voltage higher than the first voltage. First end of the second transistor is electrically separated from the first end of the first transistor. Gate and second end of the first transistor, gate of the second transistor, and second end of the third transistor are electrically connected to one another. Second end of the second transistor, gate of the third transistor, and second end and gate of the fourth transistor are electrically connected to one another.

Abstract: A data storage method applying to a phase change memory and the phase change memory are provided. After obtaining to-be-stored data, the phase change memory (PCM) generates an erase pulse signal and a write pulse signal according to the to-be-stored data. The to-be-stored data is multi-bit data. The write pulse signal includes at least two contiguous pulses. Intervals between the at least two contiguous pulses are the same. The intervals between the at least two contiguous pulses have a value determined according to the to-be-stored data. The PCM applies the erase pulse signal to a storage unit of the PCM to enable the storage unit to change to a crystalline state. Further, the write pulse signal is applied to the storage unit to enable the storage unit to change to an amorphous state corresponding to a first resistance value, where the amorphous state represents the to-be-stored data.

Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory device may maintain a digit line voltage at a ground reference for a duration associated with biasing a ferroelectric capacitor of a memory cell. For example, a digit line that is in electronic communication with a ferroelectric capacitor may be virtually grounded while a voltage is applied to a plate of the ferroelectric capacitor, and the ferroelectric capacitor may be isolated from the virtual ground after a threshold associated with applying the voltage to the plate is reached. A switching component (e.g., a transistor) that is in electronic communication with the digit line and virtual ground may be activated to virtually ground the digit line and deactivated to isolate the digit line from virtual ground.

Abstract: In an aspect of the disclosure, a method and an apparatus are provided. The apparatus may be a content addressable memory. The content addressable memory includes a plurality of memory sections each configured to store data. Additionally, the content addressable memory includes a comparator configured to compare the stored data in each of the plurality of memory sections with search input data. The comparison may be in a time division multiplexed fashion. The comparator may be configured to compare the stored data in each of the plurality of memory sections with search input data in a corresponding one of a plurality of memory access cycles. The content addressable memory may include a state machine configured to control when the comparator compares the stored data in each of the plurality of memory sections with search input data based on a state of the state machine.

Abstract: The present disclosure relates to a method of a non-volatile one time programmable memory (OTPM) including parallel programming of all banks of the OTPM by programming two rows per bank at a time, verifying the programming by comparing a first row of the two rows per bank, and verifying the programming by comparing a second row of the two rows per bank.

Abstract: A system of processing a task based on information of frequently used algorithms learned through a memory unit includes a first memory, a second memory, a processor, and a reading unit. The processor processes a first type of task using a first algorithm, and writes to a first memory cell of the second memory. The second memory including first and second memory cells each having a charge storage element. The first and second memory cells correspond to the first and second algorithms, respectively. The reading unit senses a first voltage stored in the first memory cell and a second voltage stored in the second memory cell, and provides information of frequently used algorithms to the processing device based on the sensed first and second voltages.