Abstract: A constant-transconductance rail-to-rail CMOS input circuit with offset trim is provided. PMOS and NMOS differential trim stages are scaled versions of PMOS and NMOS input stages respectively. The differential trim stages are configured to adjust the offset of the differential output current with accuracy over temperature. A first current mirror circuit is configured to receive a fraction of a bias current (?I), where ? is related to the input common mode voltage. A second current mirror circuit is configured to receive another fraction of the bias current ((1??)I). The first current mirror circuit is configured to provide current ?I to the PMOS input stage, and a scaled-down version of current ?I to the PMOS differential trim stage. The second current mirror circuit is configured to provide current ((1??)I) to the NMOS input stage, and a scaled-down version of current ((1??)I) to the differential PMOS trim stage.

Abstract: A compensation scheme for differential- or single-input transconductance amplifiers relies on an active feedback path with a resistive pole-splitting compensation circuit. The resistive compensation circuit causes pole-splitting of the two dominant poles, moving one pole to a slightly lower frequency and the other to a much higher frequency compared to the dominant poles of the uncompensated amplifier. A DC-blocking capacitor may also be placed in series with the resistor of the compensation circuit to allow for proper biasing of the circuit. By selecting appropriate values for the passive elements in the compensation circuit, the compensation scheme of the present invention can cause the amplifier to operate in a stable, linear manner over the same or even a larger bandwidth than an equivalent amplifier without compensation. The present invention does not suffer the problems of standard narrowbanding compensation schemes associated with high frequency cut-off.