Abstract: A semiconductor device and a method of forming the same is disclosed. The semiconductor device includes a substrate, a first well region disposed within the substrate, a second well region disposed adjacent to the first well region and within the substrate, and an array of well regions disposed within the first well region. The first well region includes a first type of dopants, the second well region includes a second type of dopants that is different from the first type of dopants, and the array of well regions include the second type of dopants. The semiconductor device further includes a metal silicide layer disposed on the array of well regions and within the substrate, a metal silicide nitride layer disposed on the metal silicide layer and within the substrate, and a contact structure disposed on the metal silicide nitride layer.

Abstract: A semiconductor device includes a first stack group having first interlayer insulating layers and first gate layers, alternately and repeatedly stacked on a substrate and a second stack group comprising second interlayer insulating layers and second gate layers, alternately and repeatedly stacked on the first stack group. Separation structures pass through the first and second stack groups and include a first separation region and a second separation region. A vertical structure passes through the first and second stack groups and includes a first vertical region and a second vertical region. A conductive line is electrically connected to the vertical structure on the second stack group. A distance between an upper end of the first vertical region and an upper surface of the substrate is greater than a distance between an upper end of the first separation region and an upper surface of the substrate.

Abstract: A semiconductor device includes a vertical pattern in a first direction, interlayer insulating layers, spaced apart, a side surface of each of the interlayer insulating layers facing a side of the vertical pattern, a gate electrode between the interlayer insulating layers, a side of the gate electrode facing the side of the vertical pattern, a dielectric structure between the vertical pattern and the interlayer insulating layers with the gate electrode between the interlayer insulating layers, and data storage patterns between the gate electrode and the vertical pattern, the data storage patterns spaced apart. The dielectric structure includes a first and a second dielectric layers, the second dielectric layer between the first dielectric layer and the vertical pattern. The data storage patterns are between the first dielectric layer and the second dielectric layer. The first dielectric layer includes portions between the data storage patterns and the gate electrode.

Abstract: A semiconductor device includes a substrate. A gate insulating film is formed on the surface of the substrate. A first gate electrode layer is formed on the gate insulating film. A second gate electrode layer is formed on the first gate electrode layer and electrically connected to the first gate electrode layer. A first contact extends through the second gate electrode layer to reach the first gate electrode layer. First and second impurity layers are formed on opposite sides of the first and second gate electrode layers.

Abstract: A memory device includes a substrate, a first dielectric structure, a second dielectric structure, a channel structure, a source structure, and a drain structure. The first dielectric structure and the second dielectric structure are disposed on the substrate, and are spaced apart from each other in a first direction. The channel structure interconnects the first dielectric structure and the second dielectric structure. The source structure and the drain structure are on opposite ends of the channel structure, and are respectively embedded in the first dielectric structure and the second dielectric structure, wherein a ratio in length along the first direction of the source structure to the first dielectric structure is between 0.3 and 0.4.

Abstract: A wide-band gap semiconductor device and a method of manufacturing the same are provided. The wide-band gap semiconductor device of the disclosure includes a substrate, an epitaxial layer, an array of merged PN junction Schottky (MPS) diode, and an edge termination area surrounding the array of MPS diode. The epitaxial layer includes a first plane, a second plane, and trenches between the first plane and the second plane. The array of MPS diode is formed in the first plane of the epitaxial layer. The edge termination area includes a floating ring region having floating rings formed in the second plane of the epitaxial layer, and a transition region between the floating ring region and the array of MPS diode. The transition region includes a PIN diode formed in the plurality of trenches and on the epitaxial layer between the trenches.

Abstract: A manufacturing method of a semiconductor device includes forming a contact opening in a wafer. The wafer includes a substrate, a gate structure over the substrate and a dielectric layer over the substrate and surrounding the gate structure, and the contact opening passes through the dielectric layer and exposes the substrate. A recess is formed in the substrate such that the recess is connected to the contact opening. An oxidation process is performed to convert a portion of the substrate exposed in the recess to form a protection layer lining a sidewall and a bottom surface of the recess. The protection layer is etched back to remove a first portion of the protection layer in contact with the bottom surface of the recess of the substrate. A metal alloy structure is formed at the bottom surface of the recess of the substrate.

Abstract: The vertical-conduction electronic power device is formed by a body of wide band gap semiconductor which has a first conductivity type and has a surface, and is formed by a drift region and by a plurality of surface portions delimited by the surface. The electronic device is further formed by a plurality of first implanted regions having a second conductivity type, which extend into the drift region from the surface, and by a plurality of metal portions, which are arranged on the surface. Each metal portion is in Schottky contact with a respective surface portion of the plurality of surface portions so as to form a plurality of Schottky diodes formed by first Schottky diodes and second Schottky diodes, wherein the first Schottky diodes have, at equilibrium, a Schottky barrier having a height different from that of the second Schottky diodes.

Abstract: A method for manufacturing a semiconductor device includes forming, on first and second impurity layers on a termination region side, an insulating layer, forming a first metal film and a second metal film in this order on the insulating layer and a drift layer, performing dry etching on the first and second metal films all together so that a position of a first end of a metallized layer, which is a remaining part of the first metal film, in the interface region on the termination region side and a position of a second end of an electrode, which is a remaining part of the second metal film, in the interface region on the terminal region side are the same in plan view. The first and second ends are closer to the active region than an end of the second impurity layer on the termination region side in plan view.

Abstract: A thin-film storage transistor formed in a memory array above a planar surface of a semiconductor substrate, includes (a) first and second planar dielectric layers, each being substantially parallel the planar surface of the semiconductor substrate; (b) a first semiconductor layer of a first conductivity having an opening therein; (c) second and third semiconductor layers of a second conductivity type opposite the first conductivity type, located on two opposite sides of the first semiconductor layer; (d) a charge-storage layer provided in the opening adjacent and in contact with the first semiconductor layer; and (e) a first conductor provided in the opening separated from the first semiconductor layer by the charge storage layer, wherein the first, second and third semiconductor layers are each provided as a planar layer of materials between the first and second dielectric layers.

Abstract: A method of manufacturing a semiconductor device includes: forming a trench in a semiconductor layer of first conductivity type; in the trench, forming a first layer containing silicon and then forming a second layer containing first oxide or nitride on the first layer or forming the second layer and then forming the first layer on the second layer; and thermally oxidizing the first layer.

Abstract: A vertical structure extends through a tiered structure of alternating conductive and insulative materials. The vertical structure includes a channel structure and a tunneling structure. At least one of the conductive materials of the tiered structure provides a select gate tier (e.g., including a control gate for a select gate drain (SGD) transistor). Adjacent the select gate tier of the tiered structure, the tunneling structure consists of or consists essentially of an oxide-only material. Adjacent the word line tiers of the tiered structure, the tunneling structure comprises at least one material that is other than an oxide-only material, such as a nitride or oxynitride. The oxide-only material adjacent the select gate tier may inhibit unintentional loss of charge from a neighboring charge storage structure, which may improve the stability of the threshold voltage (Vth) of the select gate tier.

Abstract: A semiconductor device includes a stacked body including a conductive pattern and an insulating pattern, a cell plug passing through the stacked body, a semiconductor layer, a peripheral transistor arranged on the semiconductor layer, a first conductor coupling the peripheral transistor to the cell plug, a second conductor coupled to the conductive pattern, a pass plug coupled to the second conductor, and a pass gate surrounding the pass plug, wherein the pass gate is arranged at substantially a same level as the semiconductor layer.

Abstract: A semiconductor device includes a Schottky diode on a silicon-on-insulator (SOI) substrate. The Schottky diode includes a guard ring with a first guard ring segment contacting a barrier region on a first lateral side of the barrier region, and a second guard ring segment contacting the barrier region on a second, opposite, lateral side of the barrier region. The first and second guard ring segments extend deeper in the semiconductor layer than the barrier region. The Schottky diode further includes a drift region contacting the barrier region, and may include a buried layer having the same conductivity type as the barrier region, extending at least partway under the drift region. The barrier region is isolated from the substrate dielectric layer of the SOI substrate by an isolation region having the same conductivity type as the guard ring. A metal containing layer is formed on the barrier region.

Abstract: A microelectronic device includes decks comprising alternating levels of a conductive material and an insulative material, the decks comprising pillars including a channel material extending through the alternating levels of the conductive material and the insulative material, a conductive contact between adjacent decks and in electrical communication with the channel material of the adjacent decks, and an oxide material between the adjacent decks, the oxide material extending between an uppermost level of a first deck and a lowermost level of a second deck adjacent to the first deck. Related electronic systems and methods of forming the microelectronic device and electronic systems are also disclosed.

Abstract: Disclosed are embodiments of a transistor (e.g., a III-V high electron mobility transistor (HEMT), a III-V metal-insulator-semiconductor HEMT (MISHEMT), or the like) that has multiple self-aligned terminals. The self-aligned terminals include a self-aligned gate, a self-aligned source terminal and, optionally, a self-aligned drain terminal. By forming self-aligned terminals during processing, the separation distances between the terminals (e.g., between the gate and source terminal and, optionally, between the gate and drain terminal) can be reduced in order to reduce device size and to improve performance (e.g., to reduce on resistance and increase switching speeds). Also disclosed herein are method embodiments for forming such a transistor.

Abstract: A semiconductor device includes a substrate. The device includes a stacked film that includes a plurality of first electrode layers provided over the substrate and separated from each other in a first direction perpendicular to a front surface of the substrate and a plurality of second electrode layers provided over the first electrode layer and separated from each other in the first direction. The device further includes a first insulating film and a second insulating film that penetrate the plurality of first electrode layers and the plurality of second electrode layers in the first direction. The stacked film further includes a first gap portion including a first portion provided between the substrate and a lowermost layer of the plurality of first electrode layers and a second portion connected to the first portion, penetrating the plurality of first electrode layers in the first direction, between the first insulating film and the second insulating film.

Abstract: A semiconductor device includes: a semiconductor substrate; a first gate trench and a second gate trench both extending from a first main surface of the semiconductor substrate into the semiconductor substrate; a semiconductor mesa delimited by the first and second gate trenches; and a field plate trench extending from the first main surface through the semiconductor mesa. The field plate trench includes a field plate separated from each sidewall and a bottom of the field plate trench by an air gap. The field plate is anchored to the semiconductor substrate at the bottom of the field plate trench by an electrically insulative material that occupies a space in a central part of the field plate, the electrically insulative material spanning the air gap to contact the semiconductor substrate at the bottom of the field plate trench. Methods of producing the semiconductor device are also described.

Abstract: A semiconductor device includes: a first electrode; a first semiconductor layer; a first insulating film extending downward from an upper surface of the first semiconductor layer, the first insulating film being columnar; a second electrode located in the first insulating film, the second electrode extending in a vertical direction, the second electrode being columnar; a second semiconductor layer partially provided in an upper layer portion of the first semiconductor layer, the second semiconductor layer being next to the first insulating film with the first semiconductor layer interposed; a third semiconductor layer partially provided in an upper layer portion of the second semiconductor layer; and a third electrode located higher than the upper surface of the first semiconductor layer, the third electrode overlapping a portion of the first insulating film, a portion of the first semiconductor layer, and a portion of the second semiconductor layer when viewed from above.

Abstract: A semiconductor device having an improved junction termination extension region is provided. The disclosure particularly relates to diodes having such an improved junction termination extension. The semiconductor device includes an active area extending in a first direction, and a junction termination extension, ‘JTE’, region of a first charge type surrounding the active area. The JTE region includes a plurality of field relief sub-regions that each surround the active area and that are mutually spaced apart in a direction perpendicular to a circumference of the active area. The plurality of field relief sub-regions includes a first group of field relief sub-regions, and for each field relief sub-region of the first group, a plurality of field relief elements of a second charge type is provided therein, which field relief elements are mutually spaced apart in a circumferential direction with respect to the active area.