Patents Examined by Khoa Doan
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Patent number: 10909005Abstract: The Object-Level Metadata-Preserving Cross Heterogeneous Operating Systems Backup And Restore Apparatuses, Methods And Systems (“MPBR”) transforms pairing request, backup request, restore request inputs via MPBR components into pairing response, backup response, restore response outputs. A device pairing request associated with a source share at a source device is obtained. A simulated block device backup volume for the source share is created on a backup device and formatted using a file system driver executable by the backup device's operating system. A backup request associated with the source share is obtained. A connection is established between the backup device and the source device using a file sharing protocol driver configured such that files metadata is presented to the backup device in a compatible metadata format. Files from the source share are synchronized. Changed synchronized files are determined. Metadata associated with the changed files is updated. A snapshot of the volume is generated.Type: GrantFiled: February 25, 2019Date of Patent: February 2, 2021Assignee: Datto, Inc.Inventors: Giovanni Roberto Carvelli, Chad A. Kosie
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Patent number: 9135182Abstract: A cache memory provided in the central processing unit is configured to include a data field which stores data in a main memory unit, a tag field which stores management information on data stored in the data field, and a valid bit which stores information about whether the data stored in the data field and the management information stored in the tag field are valid or invalid. Nonvolatile memory cells are used as memory cells which are components of the data field, the tag field, and the valid bit. Further, a power controller is provided for the central processing unit, and the power controller is configured to selectively supply power supply voltage to the data field, the tag field, and the valid bit when the cache memory is accessed from an arithmetic unit provided in the central processing unit.Type: GrantFiled: May 29, 2013Date of Patent: September 15, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Yutaka Hara
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Patent number: 9092159Abstract: Raw data is accessed from a storage device. A sample survey technique is used on the raw data to select a sample data. A data science technique is used on the sample data to determine a sample data category. The raw data is classified at least in part by considering the sample data category. A tier of storage is identified for the raw data on the storage device based on the classification.Type: GrantFiled: April 30, 2013Date of Patent: July 28, 2015Assignee: EMC CorporationInventor: Kenneth J. Taylor
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Patent number: 9081664Abstract: According to one embodiment, a memory system includes a memory unit, a first controller, and a second controller. In the memory unit, first to fourth levels (first level<second level<third level<fourth level) are written based on first and second data. The first controller comprises a first write mode of writing the fourth level based on the data of the second page and then writing the second and third levels and a second write mode of writing the third and fourth levels and then writing the second level. The second controller issues at least one of second and third commands to be supplied to the first controller in order to select at least one of the first and second write modes.Type: GrantFiled: November 27, 2012Date of Patent: July 14, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Shingo Tanimoto, Hidetaka Tsuji
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Patent number: 9063880Abstract: A write DMA includes a write unit, a read unit and a parity generation unit. The read unit reads parity data from one of two NAND flashes storing the parity data therein. The parity generation unit generates parity data based on the read parity data and a plurality of stripes obtained by dividing user data. The write unit writes a stripe into any of a plurality of NAND flashes storing stripes therein, and writes generated parity data into the other NAND flash from which parity data is not read.Type: GrantFiled: October 5, 2012Date of Patent: June 23, 2015Assignee: FUJITSU LIMITEDInventors: Yoko Kawano, Terumasa Haneda, Atsushi Uchida
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Patent number: 9047092Abstract: A load store pipeline 18 includes an issue queue 20 and load store circuitry 24. The load store circuitry 24 includes the plurality of access slot circuits 26 to 40. Dependency tracking circuitry 42, 44, 46, 48 serves to track a freeable number of access slot circuits 26 to 42 corresponding to the sum of access slot circuits that are empty and those processing data access instructions which have not bypassed any preceding data access instructions within the program execution order.Type: GrantFiled: December 21, 2012Date of Patent: June 2, 2015Assignee: ARM LimitedInventors: Mélanie Emanuelle Lucie Teyssier, Philippe Pierre Maurice Luc, Albin Pierick Tonnerre
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Patent number: 8972649Abstract: A generator matrix is provided to generate codewords from messages of write operations. Rather than generate a codeword using the entire generator matrix, some number of bits of the codeword are determined to be, or designated as, stuck bits. One or more submatrices of the generator matrix are determined based on the columns of the generator matrix that correspond to the stuck bits. The submatrices are used to generate the codeword from the message, and only the bits of the codeword that are not the stuck bits are written to a memory block. By designating one or more bits as stuck bits, the operating life of the bits is increased. Some of the submatrices of the generator matrix may be pre-computed for different stuck bit combinations. The pre-computed submatrices may be used to generate the codewords, thereby increasing the performance of write operations.Type: GrantFiled: October 5, 2012Date of Patent: March 3, 2015Assignee: Microsoft Technology Licensing, LLCInventors: John D. Davis, Parikshit Gopalan, Mark S. Manasse, Karin Strauss, Sergey Yekhanin