Abstract: A method of calculating an individual progressive lens creates one or more basic designs for lenses based on theoretical specifications, and then creates starting designs from these basic designs. Individual progressive lenses are calculated from the starting designs corresponding to the individual data from wearing test subjects. Valid starting designs are then created for production. The individual lenses are calculated from the starting designs according to individual customer data.

Abstract: A hardware emulator having a variable input emulation group is described. Each emulation group comprises two or more processors, where one of the processors (a first processor) is coupled to a data input selector and another one of the processors (a second processor) processes a first amount of data received from a data array. The data input selector receives the first amount of data and a second amount of data from the data array, and selects a third amount of data from among the first and second amounts of data. The third amount of data is provided to the first processor for evaluation.

Abstract: A data backup system is provided for backing up data files from a data source and for securing those data files against accidental modification or deletion. The system comprises storage and a data protection component that includes an application programming interface defining a command set. The system can also comprise a backup application that is configured to use the commands of the command set. The data protection component allows applications that use the commands of the command set, such as the backup application, to access the storage of the system. The data protection component prevents operating systems and applications that do not use the commands of the command set from accessing the storage. The data protection function of the data protection component can optionally be disabled to allow open access to the storage.

Abstract: Memory consistency is provided in an emulated processing environment. A processor architected with a weak memory consistency emulates an architecture having a firm memory consistency. This memory consistency is provided without requiring serialization instructions or special hardware.

Abstract: The operation of an electronic system comprising a plurality of integrated circuits or other circuit elements is simulated using a software-based development tool that provides a generic framework for simultaneous simulation of multiple circuit elements having potentially different clock speeds, latencies or other characteristics. One or more interfaces provided in the software-based development tool permit registration of processing events associated with one or more of the circuit elements. The software-based development tool is further operative to determine a system clock for a given simulation, and to schedule execution of the associated processing events in a manner that takes into account differences between the system clock and one or more circuit element clocks, so as to maintain consistency in the execution of the processing events relative to the determined system clock.

Abstract: Methods, apparatus and systems are provided that enable the generation of random regression suites for verification of a hardware or software design to be formulated as optimization problems. Solution of the optimization problems using probabilistic methods provides information on which set of test specifications should be used, and how many tests should be generated from each specification. In one mode of operation regression suites are constructed that use the minimal number of tests required to achieve a specific coverage goal. In another mode of operation regression suites are constructed so as to maximize task coverage when a fixed number of tests are run or within a fixed cost.

Abstract: Techniques for unified management communications for virtual systems are described. An apparatus may comprise a first server emulated using a first virtual machine, a second server emulated using a second virtual machine, and a virtual machine monitor. The virtual machine monitor may communicate information with one or more emulated servers using a Simple Object Access Protocol (SOAP) message. Other embodiments are described and claimed.

Abstract: An initial graph of nodes is created within a routing space, and the number and locations of the nodes in the graph are adjusted. Links are created between nodes of the graph, and traces between specified nodes are created through the linked graph.

Abstract: System, methods and apparatii are provided for emulating the performance effect on network traffic flow traversing a node in a communications network. According to one illustrative embodiment, a method of emulating the performance effect on network traffic through a node is provided that includes generating foreground traffic through the node; simulating background traffic at the node; determining an effect of the background traffic on the foreground traffic; and making a forwarding decision with respect to the foreground traffic based on the effect.

Abstract: Emulation systems and method involving invalidating blocks of translated code in emulation of a target system on a host system in are disclosed. One or more blocks of target system code are translated by the host system to produce one or more corresponding blocks of translated code. The host system uses one or more native target system instructions as hints to invalidate or potentially invalidate one or more blocks of translated code. Blocks containing such hints cause the host system to mark some or all of the one or more blocks of translated code as potentially invalid. The potentially invalid blocks may be re-translated immediately. Alternatively, the potentially invalid blocks may be checked to see if the code in these blocks has been modified. If the code has been modified, corresponding blocks of target code may be re-translated.

Abstract: A digital system design method uses a higher programming language. In order to realize a digital system, an algorithm is verified based on a program written by the higher programming language and a program is programmed considering the higher programming language-hardware characteristics before the program is written in the lower programming language, and thus conversion into the lower programming language may be easily performed.

Abstract: A computer system simulation method starts with algorithmically implementing a specification model independently of hardware architecture. High level functional blocks representing hardware components are connected together using a bus architecture-independent generic channel. The bus architecture-independent generic channel is annotated with timing and protocol details to define an interface between the bus architecture-independent generic channel and functional blocks representing hardware components. The interface is refined to obtain a CCATB for communication space. The read( ) and write( ) interface calls are decomposed into several method calls which correspond to bus pins to obtain observable cycle accuracy for system debugging and validation and to obtain a cycle accurate model.

Abstract: A method and a device for simulating an automation system are disclosed. The aim of the invention is to allow an automation system to be simulated in such a way that simulation components operating at very different computing speeds can be combined into an overall simulation. Said aim is achieved by a method comprising a control component that can be clocked using an external timing source and at least one simulation component which can be clocked using an external timing source. A coordinated clock system is provided for the control component and the at least one simulation component by means of a control component-independent timing coordinator.

Abstract: Various tools and techniques are provided for reducing an original circuit network into a simpler, realizable RCLM circuit network. Branches of the original network are merged to reduce its total number of nodes. More particularly, the branches of the original circuit are merged so that the resulting reduced circuit approximately replicates the timing characteristics of the original circuit over the desired operating frequency range. The determination whether to merge two branches is made based upon one or more circuit characteristics associated with the node connecting the branches.

Abstract: A system and method for implementing a unified model for integration systems is presented. A user provides inputs to an integrated language engine for placing operator components and arc components onto a dataflow diagram. Operator components include data ports for expressing data flow, and also include meta-ports for expressing control flow. Arc components connect operator components together for data and control information to flow between the operator components. The dataflow diagram is a directed acyclic graph that expresses an application without including artificial boundaries during the application design process. Once the integrated language engine generates the dataflow diagram, the integrated language engine compiles the dataflow diagram to generated application code.

Abstract: Initial assumptions related to the service life of a particular item, such as a component section of a building, are mathematically modeled to construct an initial lifecycle condition relationship as condition index (CI) v. time. To update the model, empirical data may be input at any time. As modeled in an engineering management system, for example, inspections are performed on the item to verify actual condition with that predicted. Quantitative inspection data are then used to update the initial curve. As inspections are performed and data recorded, the curve is updated to accurately capture observed condition and provide realistic estimates of predicted condition, and expected service life. In select embodiments of the present invention, empirical data, such as that from inspections, are weighted, e.g., inspection data may be weighted based on type, level of detail, time in service, time since last inspection and the like.

Abstract: A hardware accelerator includes hardware support for a combinational only cycle and a latch only cycle in a simulation model with a single partition of latches and combinational logic. Preferred embodiments use a special 4-input 1-output function unit in the hardware accelerator in place of the normal latch function that write back the old latch value for combinational only cycles. Other embodiments include hardware support for separate array write disables for arrays and transparent latches depending on whether the cycle is a combinational only cycle and a latch only cycle. A conditional array write disable dependent on the occurrence of a hardware breakpoint is also included that supports switching from a latch plus combinational cycle to a latch only cycle, to give control to the user before evaluating the combinational logic if a breakpoint occurs on a latch.

Abstract: A simulation system includes a simulation computer having a Web server and a client computer with an Internet browser. On the simulation computer, a process engineering process model of a technical plant is available, to which access can be made by the client computer via the Internet. In preferred embodiments, the simulation computer additionally includes an automation engineering process model of the technical plant, operation and observation software and a project engineering tool for changing the aforementioned programs in the simulation computer.

Abstract: Methods, apparatus and systems are provided that enable the generation of random regression suites for verification of a hardware or software design to be formulated as optimization problems. Solution of the optimization problems using probabilistic methods provides information on which set of test specifications should be used, and how many tests should be generated from each specification. In one mode of operation regression suites are constructed that use the minimal number of tests required to achieve a specific coverage goal. In another mode of operation regression suites are constructed so as to maximize task coverage when a fixed number of tests are run or within a fixed cost.

Abstract: According to one embodiment of the invention, a computerized method for designing a progressive die used in the manufacturing of a part formed from sheet metal includes receiving, at a computer, information regarding one or more features of the part, and determining, by the computer, a blank layout for the part based on the features of the part and the number of parts desired. The computer further determines one or more details of a strip for the blank layout, information regarding a die base based on the details of the strip, and information regarding one or more inserts for die plates of the die base based on operations of the processes needed to form the features in the part. The computerized method further includes generating, by the computer, one or more outputs associated with the progressive die.