Abstract: A connection element is arranged on a connection area of a semiconductor component. The connection element includes at least one bonding wire portion fixed on the connection area. The connection area is covered by an electrically conductive material, the fixed bonding wire portion being surrounded or embedded by the electrically conductive material.

Abstract: The present invention provides a method of fabricating an airgap-containing interconnect structure in which a patternable low-k material replaces the need for utilizing a separate photoresist and a dielectric material. Specifically, this invention relates to a simplified method of fabricating single-damascene and dual-damascene airgap-containing low-k interconnect structures with at least one patternable low-k dielectric and at least one inorganic antireflective coating.

Abstract: A semiconductor device including a substrate; a bottom electrode on the substrate; a first dielectric layer on the bottom electrode, the first dielectric layer including a first metal oxide including at least one of Hf, Al, Zr, La, Ba, Sr, Ti, and Pb; a second dielectric layer on the first dielectric layer, the second dielectric layer including a second metal oxide including at least one of Hf, Al, Zr, La, Ba, Sr, Ti, and Pb, wherein the first metal oxide and the second metal oxide are different materials; a third dielectric layer on the second dielectric layer, the third dielectric layer including a metal carbon oxynitride; and an upper electrode on the third dielectric layer.

Abstract: When external receivers are used in hearing devices there is a need to suppress feedback further. An ear mold with a receiver is therefore proposed, having a receiver connector including a first snap-fit element at the sound outlet. An adapter is inserted directly into the ear mold and has a second snap-fit element, which is snapped into the first snap-fit element in a manner such that it can be released. A seal, which surrounds the receiver connector completely, is made of a more elastic material than the receiver connector and the adapter and is fitted between the receiver connector and the adapter. It is thus possible to secure the receiver in the ear mold in an acoustically sealed manner, so that there is less feedback. The seal however also ensures that less dirt reaches the receiver.

Abstract: A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations. The intervening area comprises a trench. Conductive material is formed within the openings and against a sidewall portion of the trench to less than completely fill the trench. Covering material is formed over an elevationally outer lateral interface of the conductive material within the trench and the insulative material of the circuitry area. The insulative material within the array area is etched with a liquid etching solution effective to expose outer sidewall portions of the conductive material within the array area and to expose the conductive material within the trench. The conductive material within the array area is incorporated into a plurality of capacitors.

Abstract: A method for making back-to-front electrical connections in a wafer level chip scale packaging process is disclosed. A wafer containing a plurality of semiconductor chips is mounted on a package substrate. Each semiconductor chip in the plurality includes one or more electrodes on an exposed back side. Scribe lines between two or more adjacent chips on the wafer are removed to form relatively wide gaps. A conductive material is applied to the back side of the semiconductor chips and in the gaps. The conductive material in the gaps between two or more of the chips is then cut through leaving conductive material on the back side and on side walls of the two or more chips. As a result, the conductive material provides an electrical connection from the electrode on the back side of the chip to the front side of the chip.

Abstract: A heat generating component of a semiconductor device is located between two heavily doped semiconductor regions in a semiconductor substrate. The heat generating component may be a middle portion of a diode having a light doping, a lightly doped p-n junction between a cathode and anode of a silicon controlled rectifier, or a resistive portion of a doped semiconductor resistor. At least one thermally conductive via comprising a metal or a non-metallic conductive material is place directly on the heat generating component. Alternatively, a thin dielectric layer may be formed between the heat generating component and the at least one thermally conductive via. The at least one thermally conductive via may, or may not, be connected to a back-end-of-line metal wire, which may be connected to higher level of metal wiring or to a handle substrate through a buried insulator layer.

Abstract: An LED module A1 includes LED chips 3R, 3G, 3B, and a module substrate 1 on which the LED chips 3R, 3G, 3B are mounted. A wire 4R is connected to the LED chip 3R, and the LED chips 3G and 3B are arranged to face each other across the wire 4R. With this arrangement, the LED module A1 is reduced in size, and red light, green light and blue light are properly mixed.

Abstract: A fuse device has a fuse element provided with a first terminal and a second terminal and an electrically breakable region, which is arranged between the first terminal and the second terminal and is configured to undergo breaking as a result of the supply of a programming electrical quantity, thus electrically separating the first terminal from the second terminal. The electrically breakable region is of a phase-change material, in particular a chalcogenic material, for example GST.

Abstract: An improved system and method for assigning power and ground pins and single ended or differential signal pairs for a ball grid array semiconductor package. In certain embodiments, the system uses a hexagonal pattern where the grid may be represented by a multiplicity of nested hexagonal patterns.

Abstract: This application relates to a semiconductor device comprising a semiconductor chip, a molded body covering the semiconductor chip, wherein the molded body comprises an array of molded structure elements, and first solder elements engaged with the molded structure elements.

Abstract: Conductive oxide electrodes are described, including a bi-layer barrier structure electrically coupled with an adhesion layer, and an electrode layer, wherein the bi-layer barrier structure includes a first barrier layer electrically coupled with the adhesion layer, and a second barrier layer electrically coupled with the first barrier layer and to the electrode layer. The conductive oxide electrodes and their associated layers can be fabricated BEOL above a substrate that includes active circuitry fabricated FEOL and electrically coupled with the conductive oxide electrodes through an interconnect structure that can also be fabricated FEOL. The conductive oxide electrodes can be used to electrically couple a plurality of non-volatile re-writeable memory cells with conductive array lines in a two-terminal cross-point memory array fabricated BEOL over the substrate and its active circuitry, the active circuitry configured to perform data operations on the memory array.

Abstract: An electronic component comprising an integrated device and a plurality of packaging layers in which routing between locations on the device and lands on the surface of the component is provided by a redistribution layer. The redistribution layer may be routed below the extent of a contact pad on the surface by providing a channel through the via and redistribution layers underneath that land.

Abstract: A semiconductor light emitting structure including a substrate, a second type electrode layer, a reflecting layer, an insulating layer, a first type electrode layer, a first type semiconductor layer, an active layer and a second type semiconductor layer is provided. The second type electrode layer formed on the substrate has a current spreading grating formed by several conductive pillars and conductive walls, which are staggered and connected to each other. The reflecting layer and the insulating layer are formed on the second type electrode layer in sequence, and cover each conductive pillar and each conductive wall. The first type electrode layer, the first type semiconductor layer and the active layer are formed on the insulating layer in sequence. The second type semiconductor layer is formed on the active layer, and covers each conductive pillar and each conductive wall.

Abstract: An improved system and method for assigning power and ground pins and single ended or differential signal pairs for a ball grid array semiconductor package. In certain embodiments, the system uses a hexagonal pattern where the grid may be represented by a multiplicity of nested hexagonal patterns.

Abstract: A method of wafer level packaging includes providing a substrate including a buried oxide layer and a top oxide layer, and etching the substrate to form openings above the buried oxide layer and a micro-electro-mechanical systems (MEMS) resonator element between the openings, the MEMS resonator element enclosed within the buried oxide layer, the top oxide layer, and sidewall oxide layers. The method further includes filling the openings with polysilicon to form polysilicon electrodes adjacent the MEMS resonator element, removing the top oxide layer and the sidewall oxide layers adjacent the MEMS resonator element, bonding the polysilicon electrodes to one of a complementary metal-oxide semiconductor (CMOS) wafer or a carrier wafer, removing the buried oxide layer adjacent the MEMS resonator element, and bonding the substrate to a capping wafer to seal the MEMS resonator element between the capping wafer and one of the CMOS wafer or the carrier wafer.

Abstract: The components of a hearing apparatus and in particular of a hearing device are to be better protected against environmental influences. A hearing apparatus is thus provided with at least one acoustic converter, e.g. receiver, in a converter housing for receiving or outputting a sound, with a sound opening in the converter housing, through which or by which a sound is received or output respectively, being sealed with an airtight membrane. A pressure equalization facility is connected to the converter housing or is integrated onto the converter housing, so that the pressures on both sides of the membrane can be equalized.

Abstract: A semiconductor device which has a plurality of semiconductor chips stacked on a substrate. The semiconductor device includes semiconductor chip 2, semiconductor chip 3a stacked on substrate 4 together with semiconductor chip 2, and having a foot print larger than semiconductor chip 2, through electrode 22 extending through semiconductor chip 2 only in a central portion of semiconductor chip 2, through electrode 32 extending through semiconductor chip 3a at a position facing to through electrode 22, and conduction bump 7b arranged between through electrode 22 and through electrode 32, and conductively connecting through electrode 22 with through electrode 32.

Abstract: A power semiconductor chip (first semiconductor chip) 41 is mounted on the main surface of a first radiator plate 31, and a control IC chip (second semiconductor chip) 42 is mounted on the main surface of a second radiator plate 32. The first radiator plate 31 has an extending portion 31A extending toward the side on which the second radiator plate 32 is provided in the arrangement direction of first lead terminals (lead terminals 21 to 24). The first lead terminals (lead terminals 21 to 24) are connected to a first side of the first radiator plate 31 to function as extraction electrodes of a rear side electrode (D: drain electrode) of the power semiconductor chip 41. A second lead terminal (lead terminal 25) is connected to a bonding pad 411 serving as a source electrode (S). The third lead terminals (lead terminals 26 to 28) are connected to an electrode of the control IC chip 42.

Abstract: Various methods and apparatus for establishing thermal pathways for a semiconductor device are disclosed. In one aspect, a method of manufacturing is provided that includes providing a first semiconductor chip that has a substrate and a first active circuitry portion extending a first distance into the substrate. A barrier is formed in the first semiconductor chip that surrounds but is laterally separated from the first active circuitry portion and extends into the substrate a second distance greater than the first distance.