Abstract: The decision to prefetch inodes is based upon the detecting of access patterns that would benefit from such a prefetch. Once the decision to prefetch is made, a plurality of inodes are prefetched in parallel. Further, the prefetching of inodes is paced, such that the prefetching substantially matches the speed at which an application requests inodes.

Abstract: There is provided a method of operating a memory device comprising at least one memory module, a corresponding memory module and a memory device comprising the at least one memory module. It is proposed that in the memory module (100a, 100b, 100c, 100d) a command and write data signal (CA, WD) is received and a read data signal (RD) is transmitted from the memory module (100a, 100b, 100c, 100d). Further, an input clock signal (CLK) is received in the memory module (100a, 100b, 100c, 100d) and is regenerated by means of a clock synthesizer unit (150) of the memory module (100a, 100b, 100c, 100d) to produce a regenerated input clock signal of the memory module (100a, 100b, 100c, 100d). The read data signal (RD) transmitted from the memory module (100a, 100b, 100c, 100d) is synchronized to the regenerated input clock signal of the memory module (100a, 100b, 100c, 100d). For this purpose, the clock synthesizer unit (150) preferably comprises a phase-locked loop.

Abstract: A method, device, and system are disclosed. In one embodiment, the method comprises setting a threshold length for data allowed in a cache, inserting data into the cache during a read or a write request if the length of the data requested is less than the threshold length, and not inserting data into the cache during a read or write request if the length of the data requested is greater than or equal to the threshold length.

Abstract: A method and an apparatus to reduce network utilization for source-based snoopy cache coherent protocols have been disclosed. In one embodiment, the method includes receiving at a first processor an invalidating snoop with respect to a physical address of a portion of a memory in a multiprocessor system from a second processor, checking whether a cache of the first processor stores a copy of data associated with the physical address, and recording an identification (ID) of the second processor if the cache of the first processor stores the copy of data associated with the physical address. Other embodiments have been claimed and described.

Abstract: A memory disposition system, comprising a first memory device and a second memory device. First and second memory devices are provided to a system, such as an embedded system. The first and the second memory devices are coupled to a control unit, such as micro control unit. The first memory device stores first programs and the second memory device second programs. The first and second programs are controlled by the control unit. The first memory device can be a one time programmable memory device, such as a ROM, and the second memory device a multiple times programmable memory device, such as a flash memory.

Abstract: Briefly, in accordance with one embodiment of the invention, a portable communication device may have multiple processors and a memory. Portions of the memory may only be accessible by one of the processors.

Abstract: Apparatus, systems, methods, and articles may operate to restrict an order of processing of frames associated with a task context stored in at least one context cache memory location. The order of processing may be restricted by selectively locking the context for exclusive use by a selected lane in a multi-lane serial-attached small computer system interface (SAS) hardware protocol engine while the selected lane processes a selected one of the frames.

Abstract: A computer system provides a program access to a first register during real mode operation by using an index register and a data register, wherein the index register and the data register are located in real mode memory space and the first register is located outside of real mode memory space.

Abstract: An enhanced DRAM contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data. This data corresponds to data stored in the DRAM at a particular address. When an address is supplied to the DRAM, it is compared to the address of the data stored in the cache. If the addresses are the same, then the cache data is read at SRAM speeds. The DRAM is decoupled from this read. The DRAM also remains idle during this cache read unless the system opts to precharge or refresh the DRAM. Refresh or precharge occur concurrently with the cache read. If the addresses are not the same, then the DRAM is accessed and the embedded register is reloaded with the data at that new DRAM address.

Abstract: A system and method are disclosed for using free storage capacity on a plurality of storage media as a virtual storage device on a computer network comprising a plurality of computers. A first portion of each storage medium stores data. To implement Virtual Network Attached Storage (VNAS), the respective “free” second portions of each storage medium are aggregated into a shared storage volume. Computers on the network may mount the shared storage volume at one of a plurality of mount points and may store data on the shared storage volume. VNAS may be implemented in a peer-to-peer manner whereby each computer acts as a server for the data stored on its part of the shared storage volume (i.e., the second portion of its storage media). VNAS may be used to implement a system and method for managing data fail-over.

Abstract: A processor, capable of operation in a host machine, including memory management logic to support a plurality of memory types for a physical memory access by the processor, and virtualization support logic to determine a host memory type for a reference to a memory location by a guest in a virtual machine executable on the processor based at least in part on a memory type field stored in an entry of an extended paging table of a virtualization support system of the host machine (extended memory type field), to determine a guest memory type for the reference to the memory location, and to determine an effective memory type based on at least one of the host memory type and the guest memory type.

Abstract: A memory system has a memory controller and a plurality of memories. The plurality of memories are connected via a switch to an end of a bus, which is connected to the memory controller, wherein the plurality of memories are controlled by the switch. By suppressing reflection and loads on the bus, a higher data transmission speed can be obtained.

Abstract: A data storage apparatus includes a storage unit having a storage area. The data storage apparatus includes a read key registration unit registering a first read key that is transmitted from a first information processing apparatus and that permits reading data from the storage area; a write control unit controlling writing data in the storage unit so that writing new data in the storage area is prohibited until data stored in the storage area is read for the first time; and a read control unit controlling reading data from the storage unit so that reading data from the storage area is permitted if a second read key that is transmitted from the first information processing apparatus or a second information processing apparatus matches the first read key when reading data from the storage area is requested by the first information processing apparatus or the second information processing apparatus.

Abstract: System and methods are disclosed for load balancing Input/Output (IO) commands to be executed by one or more disk drives from an array of disk drives. Systems and methods disclosed herein use one or more properties, such as disk drive RPM, disk drive cache, command queue lengths, real-time drive data, and head position to provide load balancing of Input/Output commands.

Abstract: A memory system and a set of user-level instructions that are callable from user-level code for converting virtual addresses to physical addresses and conveying the physical addresses to peripheral devices without requiring a system call. The system uses a translation look-aside buffer (TLB) implemented in a microprocessor. The contents of the TLB can be updated while processes are executing, allowing for virtual/physical addresses to be constantly updated and loaded into the buffer without requiring that the buffer be too large. Pages in use per transaction or user-level job are “pinned down” and pinned page counts per transaction or user-level job, as well as overall counts are maintained.

Abstract: A very large virtual volume (e.g., in excess of 500 GB) is formed by distributing the disks in eleven, six-disk RAID-5 sets across the six busses of a primary local back-end controller. A spare disk is provided on each of the six busses. Each RAID-5 set is protected from the failure of a single disk by the spare disks on the busses, which can use the parity data stored in a RAID-5 set to rebuild the data stored on a failing disk and thereby restore redundancy to the RAID-5 set. Each RAID-5 set is also protected from the failure of a bus by the parity inherent in RAID-5. The RAID-5 sets are striped by a front-end controller connected to the primary local back-end controller, and the striped RAID-5 sets are presented to a host computer as a very large virtual volume. If the individual disks are 9.1 GB in size, the size of the very large virtual volume can reach 500.5 GB.

Abstract: A method is disclosed to assign addresses to a plurality of data storage devices. The method provides a switch and (N) data storage devices, where each of those (N) data storage devices is interconnected with said switch. The method further establishes (M) device addresses, where (M) is less than (N), and assigns a different one of each of the (M) device addresses to a different one of the (N) data storage devices, such that the (N) data storage devices comprise (M) address-assigned data storage devices and (P) non-address-assigned data storage devices. The method then detects a failure of the (i)th address-assigned data storage device, and transfers the (i)th address from the failed address-assigned data storage device to the (j)th data storage device, where that (j)th data storage device comprises one of the (P) previously non-addressed data storage devices.

Abstract: An improved Flash memory device, control circuit, or data handling methods is described that facilitate the moving and consolidating data in split and non-split user/overhead data sector architectures, moving and storing user and overhead data from and to separate non-volatile memory devices, differing erase blocks, or differing sectors of an erase block. This enables ECC checking and masking while moving data. In addition, the use of a split data storage approach is enabled that avoids the issue of potential corruption of both the user data and overhead data due to each being held within close proximity to each other on the same physical row by allowing user/overhead data split across two erase blocks to be easily moved, consolidated, and managed.

Abstract: One embodiment is directed to a computer system that includes primary and secondary storage systems. When a request to store a content unit is received, it may be determined whether to store the content unit on the primary storage system or the secondary storage system. In another embodiment, a computer may store information relating to an action to be performed in one of the directories of a file system that corresponds to a period of time. When the period of time to which the directory corresponds arrives, the action may be performed. In another embodiment, a content unit stored on a primary storage system may be copied to a secondary storage system in a computer system. After the content unit has been copied, the secondary storage system may send a delete request to the primary storage system to delete the content unit from the primary storage system.

Abstract: The invention comprises an apparatus and method of prefetching from a memory device having interleaved channels. The chipset prefetcher comprises a stride detector to detect a stride in a stream, a prefetch injector to insert prefetches onto the memory device, a channel mapper to map the prefetches to each channel of the memory device, a scheduler to schedule the prefetches onto the memory device in a DRAM-state aware manner, a throttling heuristic to scale the number of prefetches, and a prefetch data buffer to store prefetch data. The method of prefetching comprises tracking the state of streams, detecting a stride on one of the streams, selecting the stream with the stride for prefetch injection, enqueueing prefetches from the selected stream, mapping the prefetches to each of the interleaved channels, injecting the prefetches from the selected stream into each of the interleaved channels, and scheduling the prefetches onto the memory device in a DRAM-state aware manner.