Abstract: Short-quasi-unique-identifiers (SQUIDs) are generated and assigned to the data objects stored in memory. Pointers to a particular data object contain the data object's assigned SQUID. If a data object is moved to a second allocated memory segment, a new pointer to the second allocated memory segment is placed at the original memory segment, so that any pointers to the original memory segment now point to the new pointer. The distribution of SQUIDs is uniform. SQUIDs can be generated by counting, generated randomly, generating through some hashing mechanism, or other means. In comparing two different pointers, it is determined that the two pointers do not reference the same data object if the SQUIDs are different. On the other hand, if the SQUIDs are identical and the address fields of the two pointers are identical, then the two pointers reference the same data object.

Abstract: The present invention provides a method as well as an architecture for a host equipped with a CPU-level processing capability to access a Non-Volatile Random Access Memory (NVRAM) and at least a controller via a simple 3-wire/4-wire mechanism. The data stored in the NVRAM are shared with the controller and the host. More importantly, a multi-access mechanism further having a pragmatic bit determines the pragmatic bit for either the controller or the NVRAM. With the method of the present invention, computer system resources can be fully utilized, and thereby, peripheral devices can be easily added to the system in an inexpensive and highly efficient way.

Abstract: A data processing system and a data processor in which the control information for controlling an external device, especially, a device having a PCMCIA interface is stored in an address translation circuit for translating a first address outputted from a CPU to a second address in association with the first or second address.

Abstract: Drives of a data storage library are concurrently configured. A processor transmits library configuration data separately to each drive, initializes a first configuration process state, with a time-out period, for each drive. A drive responds with a status response, the first process state is updated to “completed”. A request for drive unique information is transmitted to the responding drive, advancing the process to a second state, with a time-out period. A drive responds with the information, and the second process state is updated to “completed”, and the received information is stored.

Abstract: Apparatus and methods to adaptively throttle accesses to memory employ a masking tool to specify the percentage of memory bandwidth available for access. The apparatus applies the mask and monitors the number of memory accesses during a throttle-monitoring window. If the number of memory accesses during the throttle-monitoring window exceeds or is fewer than the percentage of memory bandwidth specified by the mask, access to the memory continues until the end of the throttle-monitoring window. At the end of the throttle-monitoring window, the apparatus selects the next lower mask, which has a lower memory bandwidth allocation, applies the next lower mask, and monitors the number of memory accesses during the next throttle-monitoring window.

Abstract: Descriptored information is stored in a file system according to a Uniform Disk Format Specification UDF. It accommodates storage of both data and descriptor items, through separating a descriptor item from the data through storing the former in a dedicated logical sector. In particular, the descriptor items are assigned to a dedicated and immediately accessible directory space. Within the directory space, successive logical sectors are mapped at mutual stepping distances that are a factor less than a physical sector size that is uniform among data and descriptor items.

Abstract: A method of internally executing an externally initiated access to a dynamic memory array including a plurality of dynamic memory cells, wherein the dynamic memory cells require periodic refreshing, is achieved. The method comprises, first, determining if an external access to the dynamic memory array has been initiated. Second, a waiting period of RW idle time is inserted. The RW idle time comprises a sum of a row access time plus a pre-charge time. A pending refresh is performed during said RW idle time. A pending write access may be performed during the RW idle time. Finally, the external access is internally executed in the dynamic memory array after the RW idle time.

Abstract: A method, system, program, and data structure for restricting host access to at least one logical device. Each logical device comprises a section of physical storage space that is non-overlapping with the physical storage space associated with other logical devices. At least one logical device and at least one host are assigned to a cluster group. A cluster group is defined such that hosts that are not in a particular cluster group cannot access the logical devices that are assigned to the cluster group. Further, within each cluster group, a logical number is assigned to each logical device in the cluster group such that no host member of that cluster group uses the assigned logical number to access another logical device. The hosts in the cluster group use the logical number to access the logical device to which the logical number is assigned.

Abstract: A heap is a memory resource managed in units of cells and it is used in units of cells by the execution of an application program. A full garbage collection unit collects free cells based on the check result of the state of use of cells. A partial garbage collection unit collects free cells from cells that are used after the check of the state of use of cells recently made by the full garbage collection unit, based on the check result of the state of use of cells. A full/partial control unit improves the process efficiency of parallel type garbage collection by making either the full garbage collection unit or the partial garbage collection unit perform a subsequent collection of free cells based on the state of collections made in the past.

Abstract: The invention relates to cache apparatuses and a control method for managing cache memories in a multiprocessor system. A cache controller holds data which has to be invalidated for a cache coherence as data in a status where the validity is unknown, causes a cache hit in response to a reading request from a processor, provides the data as speculation data, and allows the processor to speculatively process the data. Therefore, since the data which has to be obtained from another cache or a main storage due to the invalidation is held in an Unknown status, a cache hit occurs. Thus, a data waiting time of the processor can be shortened.