Patents Examined by KiMberly Nicole McLean
  • Patent number: 6009426
    Abstract: The method combines two known types of access: access by pointer and access by variable. These two types of access are made compatible by particular rules of managing the locks: "hold", "read lock", and "write lock". Application to software platforms, in particular those used for telecommunications systems.
    Type: Grant
    Filed: April 21, 1997
    Date of Patent: December 28, 1999
    Assignee: Alcatel
    Inventors: Franck Jouenne, Dominique Guidot, Benoit Paul-Dubois Taine
  • Patent number: 5963983
    Abstract: An improved external semiconductor memory device having a work memory for storing logical address-physical address conversion information.
    Type: Grant
    Filed: April 15, 1997
    Date of Patent: October 5, 1999
    Assignee: International Business Machines Corporation
    Inventors: Tohru Sakakura, Yoshinori Sakaue
  • Patent number: 5960457
    Abstract: A test methodology for a cache memory subsystem includes setting a test unit to initiate a snoop cycle on a local bus upon lapse of a predetermined delay. The predetermined delay is initially set to a very short delay or a zero delay. The snoop cycle to be executed may take the form of an inquire cycle to a predetermined memory address. The test unit is further set or programmed to begin monitoring the local bus for certain activity including activity which is indicative of whether the snoop cycle occurred. After programming the test unit, the processor core executes a memory operation associated with the address of the snoop cycle. This memory operation causes a cache line transition. At some point, either before, during or after effectuation of the memory operation, the snoop cycle is executed by the test unit in accordance with the predetermined delay. Upon completing the memory operation, a status register is read from the test unit to determine whether the snoop cycle has yet occurred.
    Type: Grant
    Filed: May 1, 1997
    Date of Patent: September 28, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Joseph Skrovan, Royce K. Presley, Hamilton B. Carter
  • Patent number: 5937437
    Abstract: Effective-to-real address translation performance in a processor is monitored by counting selected events significant to evaluation of effective-to-real address translation in the processor to identify effective-to-real address translation bottlenecks. At least one performance monitor counter, the operation of which is controlled by a monitor mode control register, is embedded in the processor to noninvasively perform such counting. Examples of the events counted may include translation lookaside buffer misses, page table walks, or page table walk duration, taken alone or in any combination. Events lasting longer than a predetermined threshold, such as stalls lasting longer than two processor cycles, may also be selectively counted.
    Type: Grant
    Filed: October 28, 1996
    Date of Patent: August 10, 1999
    Assignee: International Business Machines Corporation
    Inventors: Charles P. Roth, Frank E. Levine
  • Patent number: 5930829
    Abstract: Allocation information for a random access memory is stored in a separate memory or memory area. Each memory block in the RAM is divided into 2.sup.n equal-sized spaces, and a memory allocation tree structure is established which stores, in a separate random access memory (which can be a dedicated, non-allocable section of the first random access memory), a single space availability indicator at a first level representing 2.sup.n equal-sized spaces, a pair of pair of space availability indicators at a second level each representing 2.sup.n-1 equal-sized spaces, and so on until a plurality of space availability indicators are placed at a suitable lower level tree structure such that each represents a single equal-sized space. When a request for allocation of memory space is made, the allocation information for a memory block is checked to determine if a space availability indicator at the level which could accommodate the request is set to the first value. (If not, a different memory block is checked.
    Type: Grant
    Filed: March 31, 1997
    Date of Patent: July 27, 1999
    Assignee: Bull HN Information Systems Inc.
    Inventor: Frank S. Little
  • Patent number: 5926826
    Abstract: An erasable programmable ROM has a storage area which is divided into blocks having a predetermined block length, each assigned a block address and provided with information. With reference to block addresses and information, the CPU specifies the blocks to be used for storing and writes a file to the ROM in block units. The CPU writes the file first to a blank block having a writing start mark written the blank block when the blank block is present or to an optional blank block if otherwise and then successively to other blank blocks. On completion of writing, the CPU searches for a blank block downstream from the last block used for writing and writes a writing start mark to the blank block found.
    Type: Grant
    Filed: March 28, 1997
    Date of Patent: July 20, 1999
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yoshihiko Ninomiya, Toshihiro Waguri
  • Patent number: 5920896
    Abstract: A computer system is equipped with an operating system having a tracer driver for generating trace data including disk locations accessed for disk accesses made by various components of the operating system during system startup/boot time. The tracer driver is loaded at an initial phase of system start-up. The computer system is further equipped with a companion disk block relocation driver for generating, if possible, an alternative disk block allocation for a current disk block allocation that will yield improved overall access time for a sequence of disk accesses. In some embodiments, the disk block relocation driver includes logic for tracing the sequence of disk accesses to determine the current disk block allocation, logic for generating the alternative disk block allocation, if possible, using the trace results, and logic for effectuating the alternate disk block allocation, if generated.
    Type: Grant
    Filed: March 21, 1997
    Date of Patent: July 6, 1999
    Assignee: Intel Corporation
    Inventors: Knut Grimsrud, Rick Coulson