Abstract: A computer memory module can include a molded layer disposed on a DRAM substrate. The molded layer can encapsulate a DRAM die and wire bonds that connect the DRAM die to the DRAM substrate, and can be shaped to include at least one cavity having a footprint sized to accommodate a system on chip (SOC) die. The DRAM module can attach to an SOC package so that the SOC die and the DRAM die are both positioned between the DRAM substrate and the SOC package, the DRAM substrate can form its electrical connections on only one side of the DRAM substrate, and the SOC die can fit at least partially into the cavity in the molded layer. This can reduce a package Z-height, compared to conventional DRAM packages in which the SOC die and the DRAM die are positioned on opposite sides of the DRAM substrate.

Abstract: At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) having an oxide level in a fin array region within a predetermined height of the oxide level of a field region. A first oxide process is performed for controlling a first oxide recess level in a field region adjacent to a fin array region comprising a plurality of fins in a finFET device. The first oxide process comprises depositing an oxide layer over the field region and the fin array region and performing an oxide recess process to bring the oxide layer to the first oxide recess level in the field region. A second oxide process is performed for controlling a second oxide recess level in the fin array region. The second oxide process comprises isolating the fin array region, depositing oxide material, and performing an oxide recess process to bring the oxide level in the fin array region to the second oxide recess level.

Abstract: Provided are methods of forming electric devices by effecting application of a stress to the device so as to deform the device within the device's elastic limit and to place the device into a new electric—e.g., resistance—state.

Abstract: A getter structure is provided, including a support; a first layer of getter material disposed on the support a second layer of getter material, the first layer of getter material being disposed between the support and the second layer of getter material; a first portion of material mechanically connecting a first face of the second layer of getter material to a first face of the first layer of getter material and forming at least one first space between the first faces of the first and second layers of getter material configured to allow a circulation of gas between the first faces of the first and second layers of getter material; and a first opening crossing through at least the second layer of getter material and emerging into the first space.

Abstract: A semiconductor device has a substrate with first and second conductive layers formed over first and second opposing surfaces of the substrate. A plurality of bumps is formed over the substrate. A semiconductor die is mounted to the substrate between the bumps. An encapsulant is deposited over the substrate and semiconductor die. A portion of the bumps extends out from the encapsulant. A portion of the encapsulant is removed to expose the substrate. An interconnect structure is formed over the encapsulant and semiconductor die and electrically coupled to the bumps. A portion of the substrate can be removed to expose the first or second conductive layer. A portion of the substrate can be removed to expose the bumps. The substrate can be removed and a protection layer formed over the encapsulant and semiconductor die. A semiconductor package is disposed over the substrate and electrically connected to the substrate.

Abstract: A semiconductor package is provided. The semiconductor package include a lower semiconductor package including a lower package substrate and a lower semiconductor chip mounted thereon, and an upper semiconductor package provided on the lower semiconductor package to include an upper package substrate and an upper semiconductor chip mounted thereon. The upper package substrate include an upper heat-dissipation pattern, the lower semiconductor chip include a first via connected to the upper heat-dissipation pattern through the lower semiconductor chip, and the first via may provide a pathway for dissipating heat generated in the lower semiconductor chip.

Abstract: In various embodiments, evaporation sources are heated and/or cooled via a fluid-based thermal management system during deposition of thin films.

Abstract: The dies of a stacked die IC are tested and, in response to detection of a defect at one of the dies, the type of defect is identified. If the defect is identified as a defective module repairable at the die itself, a redundant module of the die is used to replace the functionality of the defective module. If the defect is identified as one that is not repairable, a replacement die in the die stack is used to replace the functionality of the defective die.

Abstract: A high density fan out package structure may include a contact layer. The contact layer includes a conductive interconnect layer having a first surface facing an active die and a second surface facing a redistribution layer. The high density fan out package structure has a barrier layer on the first surface of the conductive interconnect layer. The high density fan out package structure may also include the redistribution layer, which has conductive routing layers. The conductive routing layers may be configured to couple a first conductive interconnect to the conductive interconnect layer. The high density fan out package structure may further include a first via coupled to the barrier liner and configured to couple with a second conductive interconnect to the active die.

Abstract: An image sensor chip includes a semiconductor layer intended to receive illumination on a back face and comprising a matrix of pixels on a front face. An interconnection structure is arranged on the front face and a carrier is attached to the interconnection structure with a first face of the carrier facing the front face. An annular trench, arranged on a perimeter of the image sensor chip, extends from a second face of the carrier through an entire thickness of the carrier and into the interconnection structure. A via opening, arranged within the annual trench, extends from the second face of the carrier through the entire thickness of the carrier to reach a metal portion of the interconnection structure. The via opening an annual trench are lined with an insulating layer. The via opening include a metal conductor making an electrical connection to the metal portion.

Abstract: A package assembly and a method for manufacturing the same are disclosed. The package assembly includes a leadframe having at least two groups of leads and a plurality of electronic devices arranged in at least two levels. Each group of leads is electrically coupled to a respective level of electronic devices. The package assembly further includes an interconnect for coupling one or more leads of one group of leads to one or more leads of another group of leads. The package assembly results in increased packaging density, less usage of bonding wires in the package assembly, improves reliability, and prevents possible interference.

Abstract: A method is disclosed evaluating a silicon layer crystallized by irradiation with pulses form an excimer-laser. The crystallization produces periodic features on the crystallized layer dependent on the number of and energy density ED in the pulses to which the layer has been exposed. An area of the layer is illuminated with light. A microscope image of the illuminated area is made from light diffracted from the illuminated are by the periodic features. The microscope image includes corresponding periodic features. The ED is determined from a measure of the contrast of the periodic features in the microscope image.

Abstract: Methods are provided for selectively depositing Al and N containing material on a first conductive surface of a substrate relative to a second, dielectric surface of the same substrate. In some aspects, methods of forming an Al and N containing protective layer or etch stop layer for use in integrated circuit fabrication are provided.

Abstract: An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad.

Abstract: A semiconductor device has a semiconductor chip mounted on an island of a lead frame and covered by an encapsulating resin. An outer lead extends from the encapsulating resin and is connected within the encapsulating resin to an inner lead connected to an inner lead suspension lead. A plated film is plated on the exposed surfaces of the outer lead that extend from the encapsulating resin to improve solder bonding strength of the semiconductor device onto a substrate.

Abstract: A packing method for a semiconductor device includes a step of preparing the semiconductor device that has a sealing body having a principal surface and a plurality of leads, and a step of preparing a base carrier tape that has a peripheral portion, a step portion, and a pocket portion. The method further includes a step of placing the semiconductor device in the pocket portion, a step of bonding a cover tape to the step portion in such a manner that the sealing body is pressed against the base carrier tape, and a step of winding the base carrier tape with the semiconductor device placed therein and with the cover tape bonded thereto, around a tape reel. The base carrier tape includes a principal surface of the peripheral portion, a principal surface of the step portion, and a principal surface of the pocket portion.

Abstract: The method includes the steps of: a) providing first and second layers, each including a bonding surface, at least one of said layers including recesses and the bonding surface of one of the two layers being formed at least partially of a silicon oxide film; b) bringing the bonding surfaces into contact with one another, such as to create a direct bonding interface; c) filling at least one recess with a fluid including water molecules; and d) applying a thermal budget such as to generate bond annealing. Further relating to a structure including a direct bonding interface between two bonding surfaces of two layers, the bonding surface of at least one of the layers being formed at least partially of a silicon oxide film, and the direct bonding interface includes recesses filled with a fluid including water molecules.

Abstract: An integrated circuit structure includes: a semiconductor substrate; a shallow trench isolation (STI) region in the semiconductor substrate; one or more active devices formed on the semiconductor substrate; and a resistor array having a plurality of resistors disposed above the STI region; wherein the resistor array comprises a portion of one or more interconnect contact layers that are for interconnection to the one or more active devices.

Abstract: The present invention provides a semiconductor capacitor structure. The semiconductor capacitor structure comprises a first metal layer, a second metal layer and a first dielectric layer. The first metal layer is arranged to be a part of a first electrode of the semiconductor capacitor structure, and the first metal layer comprises a first portion and a second portion. The first portion is formed to have a first pattern, and the second portion is connected to the first portion. The second metal layer is arranged to be a part of a second electrode of the semiconductor capacitor structure, and the first dielectric layer is formed between the first metal layer and the second metal layer.

Abstract: A method for critical dimension control in which a substrate is received having an underlying layer and a patterned layer formed on the underlying layer, the patterned layer including radiation-sensitive material and a pattern of varying elevation with a first critical dimension. The method further includes applying an overcoat layer over the patterned layer, the overcoat layer containing a photo agent selected from a photosensitizer generator compound, a photosensitizer compound, a photoacid generator compound, a photoactive agent, an acid-containing compound, or a combination of two or more thereof. The overcoat layer is then exposed to electromagnetic radiation, wherein the dose of electromagnetic radiation applied to different regions of the substrate is varied, and then the overcoat layer and patterned layer are heated. The method further includes developing the overcoat layer and the patterned layer to alter the first critical dimension of the patterned layer to a second critical dimension.