Patents Examined by Kripa Sagar
  • Patent number: 6962771
    Abstract: Key to the present invention is the subsequent use of two layers of different positive photoresists, possessing different exposure wavelength sensitivities. It is a general object of the present invention to provide a new and improved method of forming semiconductor integrated circuit devices, and more specifically, in the formation of self-aligned dual damascene interconnects and vias, which incorporates two positive photoresist systems, which have different wavelength sensitivities, to form trench/via openings with only a two-step etching process. In addition, the two layers of photoresist exhibit different etch resistant properties, for subsequent selective reactive ion etching steps. The use of a “high contrast” positive photoresist system has been developed wherein the resist system exposure sensitivity is optimized for wavelengths, deep-UV (248 nm) for the top layer of resist, the trench pattern, and I-line (365 nm) for the bottom layer of resist, the via pattern.
    Type: Grant
    Filed: October 13, 2000
    Date of Patent: November 8, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Shi Liu, Chih-Cheng Lin
  • Patent number: 6921630
    Abstract: A substrate material for LIGA applications w hose general composition is Ti/Cu/Ti/SiO2. The SiO2 is preferably applied to the Ti/Cu/Ti wafer as a sputtered coating, typically about 100 nm thick. This substrate composition provides improved adhesion for epoxy-based photoresist materials, and particularly the photoresist material SU-8.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: July 26, 2005
    Assignee: Sandia National Laboratories
    Inventor: Paul M. Dentinger
  • Patent number: 6905811
    Abstract: As feature sizes approach 0.1 ?m or smaller, reduction of line edge roughness (LER) becomes increasingly important. Significant reductions in edge roughness have been achieved by applying a second Ebeam exposure after the initial one that is used to define the pattern. After this second blanket exposure a longer heat treatment and a stronger development process than before are used. In addition to reducing edge roughness the disclosed treatment allows the CD to be reduced under tight control since the amount of CD reduction is proportional to the second Ebeam dosage.
    Type: Grant
    Filed: April 22, 2003
    Date of Patent: June 14, 2005
    Assignee: Headway Technologies, Inc.
    Inventors: Chao Peng Chen, Chunping Luo, Stuart Kao, Jei-Wei Chang
  • Patent number: 6902872
    Abstract: A method of manufacturing a microelectronics device is provided, wherein the microelectronics device is formed on a substrate having a frontside and a backside. The method comprises forming a circuit element on the frontside of the substrate from a plurality of layers deposited on the frontside of the substrate, wherein the plurality of layers includes an intermediate electrical contact layer, and forming an interconnect structure after forming the electrical contact layer. The interconnect structure includes a contact pad formed on the backside of the substrate, and a through-substrate interconnect in electrical communication with the contact pad, wherein the through-substrate interconnect extends from the backside of the substrate to the electrical contact layer.
    Type: Grant
    Filed: July 29, 2002
    Date of Patent: June 7, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Diane Lai, Samson Berhane, Barry C. Snyder, Ronald A. Hellekson, Hubert Vander Plas
  • Patent number: 6899993
    Abstract: An optical disk and a method of fabricating the optical disk capable of improving the signal quality and the productivity are disclosed. The optical disk includes a plurality of reflective layers stacked on a substrate, amorphous layers formed among the reflective layers which include a small amount of oxide therein, a recording layer, formed on the reflective layer, for recording information, and a cover layer formed on the recording layer.
    Type: Grant
    Filed: April 26, 2002
    Date of Patent: May 31, 2005
    Assignee: LG Electronics Inc.
    Inventors: Tae Hee Jeong, Hun Seo
  • Patent number: 6887633
    Abstract: In one embodiment, a spacing is determined for each edge of a number of features in a photolithographic design. The edges have at least a partially predictable layout. Based on the spacing and the predictable layout, a bridge structure is generated. Each bridge of the bridge structure connects one of the edges to an edge of a neighboring feature. Then, the features and the bridge structure are provided for a phase assignment. The phase assignment assigns features at opposite ends of each bridge in the bridge structure to opposite phases. In another embodiment, a sub-resolution assist feature (SRAF) is introduced for an edge of a feature and a bridge is generated from the feature to the SRAF. Then, the feature and the SRAF are assigned to opposite phases based on the relationship defined by the bridge.
    Type: Grant
    Filed: February 8, 2002
    Date of Patent: May 3, 2005
    Inventor: Chih-Hsien Nail Tang
  • Patent number: 6874262
    Abstract: A substrate having a photoresist coated thereon is exposed to exposure light along a line through a lens 1. The exposure position is moved from the initial position O1 to a position O2 that is separated from the initial position by a distance corresponding to the sum of a groove width Gw and a land width Lw. The exposure is carried out along a line parallel to the initial exposure line. By repeating this, exposed areas having a width Lw and a separation Gw are formed on the photoresist. The photoresist is developed to remove the exposed areas of the photoresist. A resin or the like is pressed on it to form a replica. From the replica, a stamper is manufactured using an electroforming method. Finally, a grooved molding substrate is manufactured from a glass or resin using the stamper. Although the land width Lw is defined by the effective spot diameter ? of the optical system, the groove width Gw can be less than this value.
    Type: Grant
    Filed: April 4, 2003
    Date of Patent: April 5, 2005
    Assignee: Nikon Corporation
    Inventors: Madoka Nishiyama, Seiji Morita
  • Patent number: 6875558
    Abstract: A method for forming a trench isolation structure on a substrate. The method includes applying a pad oxide layer (226) on the substrate (224), applying a polysilicon layer (228) over the pad oxide layer, and applying a CVD anti-reflective coating (ARC) (230) over the polysilicon layer. A photoresist is formed on the CVD ARC and a trenched is etched at a desired location. One embodiment provides a method for depositing a trench oxide filling layer (300) on the trenched substrate utilizing the surface sensitivity of dielectric materials such as O3/TEOS to achieve a substantially self-planarized dielectric layer. Prior problems with porous trench fill, particular near trench corners, are obviated by use of the polysilicon layer. After deposition, an oxidizing anneal can be performed to grow a thermal oxide (307) at the trench surfaces and densify the dielectric material. A chemical mechanical polish can be used to remove the excess oxide material, including the porous regions.
    Type: Grant
    Filed: August 16, 2000
    Date of Patent: April 5, 2005
    Assignee: Applied Materials, Inc.
    Inventors: Frederic Gaillard, Fabrice Geiger, Ellie Y. Yieh
  • Patent number: 6872494
    Abstract: A photomask for use in a semiconductor fabrication process, comprises a plurality of first mask patterns for transferring resist patterns, and second mask patterns for restraining an optical proximity effect, each having a width not larger than a resolution limit. The second mask patterns are formed in a line-like shape, and disposed so as to link together the plurality of the first mask patterns. As a result of use of the second mask patterns in the line-like shape, a fewer parameters may be added in simulation of resist patterns. Thus, it becomes possible to provide the photomask for efficiently performing simulation and forming suitable resist patterns. Further, the photomask can be used in a semiconductor fabrication process.
    Type: Grant
    Filed: May 8, 2002
    Date of Patent: March 29, 2005
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Daigo Hoshino
  • Patent number: 6872512
    Abstract: A method of forming a resist pattern effectively controls the manner/style and the amount of modification of a resist pattern in its reflowing process, realizing a desired resist pattern with a desired accuracy even if the deformation amount of the resist pattern is increased in the reflowing process. A second layer is formed on a first layer and then, a first resist pattern is formed on the second layer. The second layer is selectively etched using the first resist pattern as a mask. Thereafter, wettability of at least part of an exposed area of the second or first layer from the first resist pattern is adjusted, thereby forming a wettability-adjusted part. The first resist pattern is modified in such a way as to extend to the wettability-adjusted area by reflowing the first resist pattern using an organic solvent, thereby forming a second resist pattern for selectively etching the first layer or the second layer.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: March 29, 2005
    Assignee: NEC LCD Technologies, Ltd.
    Inventor: Masami Yamashita
  • Patent number: 6855467
    Abstract: A pattern of a transfer mask to transfer, by the use of energy beams, a transfer pattern to a substrate is disclosed, the transfer mask made by forming an aperture pattern in a thin film portion supported by a supporting frame portion. When the transfer pattern includes a shielding pattern in which one part is connected to at least the periphery of the transfer mask, a shielding pattern portion, where the ratio of the surface area of the pattern surface portion on the transfer mask to a sectional area of a supporting portion is larger than 5000, is divided and developed.
    Type: Grant
    Filed: September 4, 2001
    Date of Patent: February 15, 2005
    Assignee: Hoya Corporation
    Inventor: Isao Amemiya
  • Patent number: 6852524
    Abstract: A carrier having indexes in a probe non-fixing region is used and solutions containing probes are applied to respective specific positions on the carrier by referring to said indexes and fixed. The position of a target compound that is specifically bonded to a probe fixed to a probe carrier manufactured by a method according to the invention can be accurately and quickly detected by referring to the indexes.
    Type: Grant
    Filed: April 29, 2002
    Date of Patent: February 8, 2005
    Assignee: Canon Kabushiki Kaisha
    Inventors: Nobuyuki Okamura, Tadashi Okamoto, Makoto Kameyama
  • Patent number: 6849390
    Abstract: A stamper-forming electrode material contains Cu as its main ingredient and at least one other element, preferably Ag and/or Ti. It is preferred that the Ag content be 10.0 wt % or less and that the Ti content be 5.0 wt % or less. A stamper-forming thin film is made of this stamper-forming electrode material, whereby its corrosion resistance is improved to suppress damage to itself, and a high-quality stamper can hence be formed.
    Type: Grant
    Filed: February 4, 2002
    Date of Patent: February 1, 2005
    Assignee: Pioneer Corporation
    Inventors: Masahiro Katsumura, Tetsuya Iida, Nobuhiro Oda, Takashi Ueno
  • Patent number: 6846598
    Abstract: In order to shorten the time required to change or correct a mask pattern over a mask, light-shielding patterns formed of a resist film for integrated circuit pattern transfer are partly provided over a mask substrate constituting a photomask in addition to light-shielding patterns formed of a metal for the integrated circuit pattern transfer.
    Type: Grant
    Filed: October 17, 2003
    Date of Patent: January 25, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Norio Hasegawa, Toshihiko Tanaka, Joji Okada, Kazutaka Mori, Ko Miyazaki
  • Patent number: 6846616
    Abstract: A process for the production of a pattern-forming body, the process including the steps of disposing a catalyst-containing layer-side substrate containing at least a photo catalyst-containing layer and a pattern-forming body substrate containing a characteristic-changeable layer which is changed in characteristics by the action of the photocatalyst in at least said photocatalyst-containing layer such that the photocatalyst-containing layer is in contact with the characteristic-changeable layer followed by performing exposure to thereby change the characteristics of the exposed portion of the characteristic-changeable layer and thereafter dismounting the photocatalyst-containing layer-side substrate, thereby obtaining a pattern-forming body having a pattern which has been changed in characteristics on the characteristic-changeable layer.
    Type: Grant
    Filed: September 12, 2001
    Date of Patent: January 25, 2005
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Hironori Kobayashi, Masato Okabe, Manabu Yamamoto
  • Patent number: 6838228
    Abstract: A system and related process to enable control of photolithographic pattern features on a structure having one or more severe non-flat topologies. The system includes an analysis of the Depth of Focus associated with photolithographic equipment and a photoresist film applied to the structure. From that determination a range of layout dimension of the topologies is identified accordingly and incorporated into the fabrication of such topologies. A conformal layer of material is then applied to the formed structure including the determined topologies to effectively substantially close up the topologies prior to application of the photoresist film. The system is suitable for use with any structure having severe topologies and photolithographic limitations including, for example, in the fabrication of micro-electro mechanical systems.
    Type: Grant
    Filed: May 14, 2001
    Date of Patent: January 4, 2005
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Eric H. Johnson, Michael W. Harley-Stead
  • Patent number: 6838215
    Abstract: A method for producing a graytone mask capable of satisfying a dimensional accuracy of a predetermined graytone pattern, on a graytone mask having, at least in a part, a predetermined graytone pattern. Suppressed to ±1% or less an on-plane distribution in thickness of a resist film to be applied onto a substrate in a graytone mask producing process.
    Type: Grant
    Filed: September 26, 2002
    Date of Patent: January 4, 2005
    Assignee: Hoya Corporation
    Inventor: Kazuhisa Imura
  • Patent number: 6835503
    Abstract: The present invention relates to fabricating a reticle or mask for use in an extreme ultraviolet (“EUV”) photolithographic process. The EUV reticle comprises a substrate, a planarizing layer formed over a surface of the substrate, and a reflective layer deposited in contact with the planarizing layer. The planarizing layer comprises a material that has superior surface flatness properties and provides a flat surface upon which the reflective layer is deposited. The planarizing layer is spin-coated onto the substrate and comprises a material such as an anti-reflective material, a dielectric material, or a polymer. Since the reflective layer is deposited over the flat surface provided by the planarizing layer, the reflective layer is not compromised by defects in the surface of the substrate.
    Type: Grant
    Filed: April 12, 2002
    Date of Patent: December 28, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Anthony C. Krauth
  • Patent number: 6835534
    Abstract: The present invention discloses devices and methods relating to patterning substrates using chemical functionalization. The methods include covering the surface of a substrate with a first plurality of molecules, selecting at least one internal bond from the plurality of molecules, and reacting the at least one internal bond to form at least one second functional group. Either or both of the functional groups can then be further reacted.
    Type: Grant
    Filed: October 26, 2001
    Date of Patent: December 28, 2004
    Assignee: The Penn State Research Foundation
    Inventors: Paul S. Weiss, Ray L. Funk
  • Patent number: 6833234
    Abstract: Methods for the preparation of multilayered resists are described. To efficiently pattern large contiguous areas rapidly, a procedure has been developed using spot-size modulation of the focused laser beam to more efficiently pattern interior portions. Critical portions at the perimeter are patterned at high resolutions. The spot-size is progressively increased towards the interior allowing a controlled transition to coarser spot-sizes without impacting the exposure dose in critical portions. Patterning times are significantly reduced since in effect shells are patterned. An algorithm is defined to subdivide a layer into different zones, determine the appropriate focused spot-sizes used for each zone, and define the laser scan trace within a zone to enable efficient patterning of broad areas in positive tone resists.
    Type: Grant
    Filed: August 6, 2001
    Date of Patent: December 21, 2004
    Assignee: Massachusetts Institute of Technology
    Inventors: Theodore M. Bloomstein, Roderick R. Kunz, Stephen T. Palmacci