Abstract: A synchronous rectifier control apparatus includes a continuous conduction mode detection circuit configured to receive a voltage across a synchronous rectifier switch and determine whether the synchronous rectifier switch operates in a continuous conduction mode based on a rising slope of the voltage across the synchronous rectifier switch, a turn-off timer control circuit configured to measure a conduction time of the synchronous rectifier switch and turn off the synchronous rectifier switch after the conduction time of the synchronous rectifier switch in a current cycle is substantially equal to the conduction time measured in an immediately previous cycle, and a drive voltage control circuit configured to reduce a gate drive voltage of the synchronous rectifier switch after the conduction time of the synchronous rectifier switch in the current cycle is substantially equal to the conduction time measured in the immediately previous cycle multiplied by a predetermined percentage.

Abstract: AC to DC power supplies are disclosed. One AC to DC power supply includes a transformer having a primary side and a secondary side and a passive rectifier coupled to the secondary side of the transformer. The passive rectifier is configured to rectify AC power at the secondary side to DC power at an output of the rectifier. An active rectifier is configured to control voltages applied to the primary side of the transformer to induce a non-sinusoidal voltage at the secondary side of the transformer and a sinusoidal current drawn by the passive rectifier. An isolating DC-to-DC converter is coupled between the active rectifier and the output of the passive rectifier to magnetically couple power from the active rectifier to the output of the passive rectifier while galvanically isolating the active rectifier from the output of the passive rectifier.

Abstract: The present disclosure concerns a device including a first switch, a diode, and a passive resistive element electrically in series between conduction and control terminals of the first switch, a terminal of the diode located on the side of the first switch being coupled to a node of application of a potential variable with respect to the potential of said conduction terminal.

Abstract: A minimum number of levels required to output a target modulation ratio is determined. Additionally, determining a total number of voltage orders to be controlled among a voltage fundamental wave and harmonics of power converter, comparing the minimum number of levels and the total number of voltage orders to be controlled, and fixing a larger one as a number of switching times in a quarter cycle for the target modulation ratio are performed. Further, when the total number is fixed, a shape of an output voltage is determined, and based on the target modulation ratio and the number of switching times in the quarter cycle, a determination of switching phases is made, in addition to a derivation of the pulse pattern for one cycle by which each output voltage level is used according to the target modulation ratio and the output voltage shape, and the phase is determined.

Abstract: A hysteretic current control switching power converter with a clock-controlled switching frequency is disclosed. A power converter includes a switching circuit including a high side switch and a low side switch coupled to one another at a switching node, with an inductor being coupled between the switching node and a regulated supply voltage node. The power converter further includes a control circuit configured to alternately cause activation of the high side switch and the low side switch, wherein the control circuit is configured to activate the low side switch in response to a first voltage reaching peak threshold value, the first voltage corresponding to a current through the inductor. A ramp voltage circuit is configured to, in response to a clock signal, generate a ramp voltage, wherein the peak threshold value is based on the ramp voltage.

Abstract: A power conversion device includes a power supply, a converter, a current detection circuit, and a control circuit. The power supply includes positive and negative terminals. The converter includes a primary side and a secondary side. The converter is configured to output a first current to a load. The primary side is electrically connected to the positive terminal and the negative terminal of the power supply in parallel. The secondary side is electrically connected to the positive terminal of the power supply and the load in series. The current detection circuit is coupled between the secondary side and the load, and is configured to detect the first current to output a current detection signal. The control circuit is coupled to the current detection circuit for outputting a control signal to the converter according to the current detection signal and a reference current signal.

Abstract: A linear voltage regulator includes a voltage input and a voltage output. The linear voltage regulator includes a buffer having a voltage node, an input node, an output node and a control node and a power transistor having a control node coupled to the output node of the buffer, an input node coupled to the voltage input and an output node coupled to the voltage output. The linear voltage regulator includes a dropout detection module having a control node coupled to the control node of the power transistor, a voltage input node coupled to the voltage input, a voltage output node coupled to the voltage output and an output node. The linear voltage regulator includes a feedforward module having an input node coupled to the output node of the dropout detection module and an output node coupled to the control node of the buffer.

Abstract: A switch-mode power supply and a zero current detector for use therein. A zero current detector includes an input stage and an output stage. The output stage is coupled to the input stage. The output stage includes a detector output terminal, a first transistor, and a second transistor. The first transistor includes an input terminal and a control terminal. The input terminal is coupled to the detector output terminal. The control terminal is coupled to the input stage. The second transistor includes an input terminal, a control terminal, and an output terminal. The input terminal is coupled to the control terminal of the first transistor. The control terminal is coupled to the input terminal of the second transistor. The output terminal is coupled to ground.

Abstract: Methods and apparatuses for controlling an apparatus comprising a controller integrated in a first slave device. In an example, the controller can detect a sensed current of the first slave device. The controller can receive a voltage signal associated with a second slave device connected to the first slave device. The controller can generate a correction current based on the sensed current of the first slave device and the voltage signal. The controller can modulate a pulse width modulation (PWM) signal received by the first slave device using the correction current. The controller can control a power converter using the modulated PWM signal.

Abstract: A circuit for use in an LLC converter comprises a first primary side switch, a first secondary side switch assembly, a controller, and a resonant network. The controller is configured to measure, on the LLC primary side, a first voltage and determine a delay due to the first voltage. The controller is also configured to apply a first gate voltage to the first primary side switch to transition the first primary side switch from an off state to an on state and apply a second gate voltage to the first secondary side switch assembly to transition the first secondary side switch assembly from an off state to an on state. The application of the first and second gate voltages are separated by a synchronous rectifier delay based on the delay due to the first voltage, the first voltage comprising a voltage across the resonant capacitor.

Abstract: A voltage regulation circuit includes a switching output terminal, a high-side output transistor, a low-side output transistor, a high-side replica transistor, a low-side replica transistor, and a comparator circuit. The high-side output transistor is configured to drive the switching output terminal. The low-side output transistor is configured to drive the switching output terminal. The high-side replica transistor is coupled to the high-side output transistor. The low-side replica transistor is coupled to the high-side replica transistor and the low-side output transistor. The comparator circuit is coupled to the high-side replica transistor and the low-side replica transistor, and is configured to compare a signal received from both the high-side replica transistor and the low-side replica transistor to a ramp signal.

Abstract: A circuit for use in an LLC converter comprises a first primary side switch, a first secondary side switch assembly, and a controller. The controller is configured to measure, on the primary side of the LLC converter, a first voltage and determine, based on the first voltage, a delay due to the first voltage. The controller is also configured to apply a first gate voltage to the first primary side switch to transition the first primary side switch from an off state to an on state and apply a second gate voltage to the first secondary side switch assembly to transition the first secondary side switch assembly from an off state to an on state. The application of the first gate voltage and the application of the second gate voltage are separated by a synchronous rectifier delay based at least on the delay due to the first voltage.

Abstract: A DLDO has a configuration that mitigates performance degradation associated with limit cycle oscillation (LCO). The DLDO comprises a clocked comparator, an array of power transistors, a digital controller and a clock pulsewidth reduction circuit. The digital controller comprises control logic configured to generate control signals that cause the power transistors to be turned ON or OFF in accordance with a preselected activation/deactivation control scheme. The clock pulsewidth reduction circuit receives an input clock signal having a first pulsewidth and generates the DLDO clock signal having the preselected pulsewidth that is narrower that the first pulsewidth, which is then delivered to the clock terminals of the clocked comparator and the digital controller. The narrower pulsewidth of the DLDO clock reduces the LCO mode to mitigate performance degradation caused by LCO.

Abstract: A reference voltage circuit is disclosed. In the reference voltage circuit, a comparator compares a reference voltage and a voltage of a capacitor, so as to output a comparison signal; a controller checks conditions of the reference voltage and the leakage current based on the comparison signal; when a voltage of the capacitor is reduced too quickly, the controller adjusts a switching frequency of a switch device to effectively maintain the voltage of the capacitor.

Abstract: A power quality compensator device and a control method thereof are provided. The power quality compensator device is electrically connected to a power grid and a nonlinear load, and includes a current controller, a converter, a ripple predictor, a processing unit and a voltage controller. The current controller is configured to receive an instruction current and output a switch control signal. The converter is configured to output an output current and an actual DC bus voltage according to the switch control signal. The ripple predictor is configured to receive an intermediate voltage and a first current and output a predicted ripple voltage. The processing unit is configured to output a processing result according to the actual DC bus voltage, the predicted ripple voltage and a reference DC bus voltage. The voltage controller is configured to receive the processing result and output a voltage control signal to the current controller.

Abstract: Embodiments of an electrostatic discharge (ESD) protection device and a method for operating an ESD protection device are described. In one embodiment, an ESD protection device includes a primary ESD protection unit electrically connected to a first node and to a second node and configured to shunt current in response to an ESD pulse received between the first and second nodes and a secondary ESD protection unit electrically connected to the primary ESD protection unit and to the second node and configured to shunt current in response to the ESD pulse to keep an output voltage of the ESD protection device to be within a safe operating voltage range of a device to be protected. Other embodiments are also described.

Abstract: The invention relates to a circuit comprising a voltage reference (R) and a low-pass filter (F) electrically connected to the voltage reference (R). The filter (F) comprises a stage formed by a stage resistance (Re) electrically connected at a midpoint (M) to a stage capacitor (Ce), the stage resistance (Re) and the stage capacitor (Ce) at least partially defining a time constant of the filter and the midpoint (M) carrying the filtered reference voltage (V?ref). The circuit also comprises a transistor (T) and a control circuit (Cde) of the gate of the transistor (T) configured to bias the transistor (T) in conduction when the circuit (1) is turned on, the on-state resistance of the transistor (T) combining with the stage capacitor (Ce) to raise the filtered reference voltage (V?ref) with a settling time constant lower than the filter time constant.

Abstract: A rectifier circuit has one or more bridge circuits each with: a first leg with two diodes in series and an AC terminal at a midpoint between the two, a second leg with two semiconductor switches in parallel to the first, a third diode connected to a upper node of each leg, a fourth diode connected to a lower node of each leg, and a capacitor leg with two capacitors in series between the third and fourth diode. A midpoint between the capacitors is connected to a midpoint between the semiconductor switches. The first arrangement is two controllable semiconductor switches in series. A gate node of the second is connected to a first load terminal of the first switch and the first load terminal is connected to the lower node. The second semiconductor switch is a third controllable semiconductor switch with a gate node connected to the lower node.

Abstract: A load control device for controlling power delivered from an AC power source to an electrical load may have a closed-loop gate drive circuit for controlling a semiconductor switch of a controllably conductive device. The controllably conductive device may be coupled in series between the source and the load. The gate drive circuit may generate a target signal in response to a control circuit. The gate drive circuit may shape the target signal over a period of time and may increase the target signal to a predetermined level after the period of time. The gate drive circuit may receive a feedback signal that indicates a magnitude of a load current conducted through the semiconductor switch. The gate drive circuit may generate a gate control signal in response to the target signal and the feedback signal, and render the semiconductor switch conductive and non-conductive in response to the gate control signal.

Abstract: A switching control circuit for controlling switching of a transistor in a power supply circuit, such that the power supply circuit generates an output voltage at a target level. The switching control circuit includes an overload detection circuit detecting that a load of the power supply circuit is in an overload condition, when a voltage according to the output voltage reaches a predetermined level, an overcurrent detection circuit detecting that a load current is an overcurrent, when a current according to the load current reaches a predetermined value, an adjustment circuit decreasing the predetermined value, when a first time period has elapsed since the load becomes in the overload condition, a drive circuit driving the transistor such that the output voltage reaches the target level, and a control circuit causing the drive circuit to stop driving the transistor, after the load becomes in the overload condition or the load current becomes the overcurrent.