Patents Examined by Kyle Vallecillo
  • Patent number: 11556790
    Abstract: Apparatuses and methods can be related to implementing age-based network training. An artificial neural network (ANN) can be trained by introducing errors into the ANN. The errors and the quantity of errors introduced into the ANN can be based on age-based characteristics of the memory device.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: January 17, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Saideep Tiku, Poorna Kale
  • Patent number: 11557364
    Abstract: Disclosed herein is logic circuitry and techniques for operation that hardware to enable the construction of first-in-first-out (FIFO) buffers from latches while permitting stuck-at-1 fault testing for the enable pin of those latches, as well as testing the data path at individual points through the FIFO buffer.
    Type: Grant
    Filed: July 27, 2021
    Date of Patent: January 17, 2023
    Assignee: STMicroelectronics International N.V.
    Inventors: Venkata Narayanan Srinivasan, Balwinder Singh Soni, Avneep Kumar Goyal
  • Patent number: 11556420
    Abstract: Methods, devices, systems, and apparatus including computer-readable mediums for managing error correction coding in memory systems are provided. In one aspect, a memory system includes a system controller configured to communicate with a host device, and a memory device coupled to the system controller. The memory device includes at least one memory and a memory controller coupled to the at least one memory. The memory controller includes an error correction code (ECC) circuit configured to perform error correction coding for data received from at least one of the system controller or the at least one memory.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: January 17, 2023
    Assignee: Macronix International Co., Ltd.
    Inventors: Kuan-Chieh Wang, Shih-Chou Juan
  • Patent number: 11552733
    Abstract: Apparatuses for transmitting and receiving a signal in a communication system are provided. An apparatus of a receive device includes a receiver configured to receive, from a transmit device, a signal comprising remaining bits of parity bits after puncturing, wherein the parity bits are obtained by adding at least one shortened bit to information bits to obtain input bits for an encoding, if a number of the information bits is less than a number of the input bits for the encoding; and a hardware processor configured to determine a number of puncture bits for the parity bits, generate an output signal by adding at least one value corresponding to the number of the puncture bits to the signal, and decode the output signal.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: January 10, 2023
    Inventors: Hong-Sil Jeong, Sung-Ryul Yun, Hyun-Koo Yang, Se-Ho Myung, Alain Mourad, Ismael Gutierrez
  • Patent number: 11550662
    Abstract: The present technology relates to an electronic device. More specifically, the present technology relates to a storage device and a computing system. A storage device according to an embodiment may include a memory device including a firmware block group configured to store main firmware data and sub firmware data, and a user block group configured to store write data, and a memory controller, in response to a booting request provided from a host, configured to count a number of previously generated power losses based on data stored in an open block in the user block group in a booted state based on the main firmware data, performs a rebooting operation using the sub firmware data when the number of power losses exceeds a reference number, and execute sub firmware to correct an error of data related to the power losses.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: January 10, 2023
    Assignee: SK hynix Inc.
    Inventor: Eu Joon Byun
  • Patent number: 11550661
    Abstract: A memory includes: a data receiving circuit suitable for receiving a data during a write operation; a data rotation circuit suitable for changing an order of the data transferred from the data receiving circuit and outputting the data whose order is changed in response to an address during the write operation; an error correction code generation circuit suitable for generating an error correction code based on the data output from the data rotation circuit during the write operation; and a memory core suitable for storing the data received by the data receiving circuit and the error correction code during the write operation.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: January 10, 2023
    Assignee: SK hynix Inc.
    Inventors: Eun Hyup Doh, Man Keun Kang
  • Patent number: 11550654
    Abstract: Methods, apparatuses, and systems related to an apparatus are described. The apparatus may include (1) a fuse array configured to provide non-volatile storage of fuse data and (2) local latches configured to store the fuse data during runtime of the apparatus. The apparatus may further include an error processing circuit configured to determine error detection-correction data for the fuse data. The apparatus may subsequently broadcast data stored in the local latches to the error processing circuit to determine, using the error detection-correction data, whether the locally latched data has been corrupted. The error processing circuit may generate corrected data to replace the locally latched data based on determining corruption in the locally latched data.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: January 10, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Yuan He, Jiyun Li
  • Patent number: 11544145
    Abstract: A programmable crossbar matrix or an array of steering multiplexors (MUXs) coalesces (i.e., routes) the data values from multiple known “bad” bit positions within multiple symbols of a codeword, to bit positions within a single codeword symbol. The single codeword symbol receiving the known “bad” bit positions may correspond to a check symbol (vs. a data symbol). Configuration of the routing logic may occur at boot or initialization time. The configuration of the routing logic may be based upon error mapping information retrieved from system non-volatile memory (e.g., memory module serial presence detect information), or from memory tests performed during initialization. The configuration of the routing logic may be changed on a per-rank basis.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: January 3, 2023
    Assignee: Rambus Inc.
    Inventor: John Eric Linstadt
  • Patent number: 11537469
    Abstract: An exemplary method for reading data stored in a flash memory includes: selecting an initial gate voltage combination from a plurality of predetermined gate voltage combination options; controlling a plurality of memory units in the flash memory according to the initial gate voltage combination, and reading a plurality of bit sequences; performing a codeword error correction upon the plurality of bit sequences, and determining if the codeword error correction successful; if the codeword error correction is not successful, determining an electric charge distribution parameter; determining a target gate voltage combination corresponding to the electric charge distribution parameter by using a look-up table; and controlling the plurality of memory units to read a plurality of updated bit sequences according to the target gate voltage combination.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: December 27, 2022
    Assignee: Silicon Motion, Inc.
    Inventor: Tsung-Chieh Yang
  • Patent number: 11537471
    Abstract: A memory controller for controlling a memory operation of a memory device includes: an error correction code (ECC) circuit configured to detect an error of first read data read from the memory device and correct the error; an error type detection logic configured to write first write data to the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparing, and output information about an error type identified by the error bit; and a data patterning logic configured to change a bit pattern of input data to reduce an error of the second read data based on the information about the error type.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: December 27, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeongho Lee, Youngsik Kim, Seungyou Baek, Eunchu Oh, Youngkwang Yoo, Younggeun Lee
  • Patent number: 11537851
    Abstract: Methods and systems are disclosed using improved training and learning for deep neural networks. In one example, a deep neural network includes a plurality of layers, and each layer has a plurality of nodes. The nodes of each L layer in the plurality of layers are randomly connected to nodes of an L+1 layer. The nodes of each L+1 layer are connected to nodes in a subsequent L layer in a one-to-one manner. Parameters related to the nodes of each L layer are fixed. Parameters related to the nodes of each L+1 layers are updated. In another example, inputs for the input layer and labels for the output layer of a deep neural network are determined related to a first sample. A similarity between different pairs of inputs and labels is estimated using a Gaussian regression process.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: December 27, 2022
    Assignee: Intel Corporation
    Inventors: Yiwen Guo, Anbang Yao, Dongqi Cai, Libin Wang, Lin Xu, Ping Hu, Shandong Wang, Wenhua Cheng, Yurong Chen
  • Patent number: 11533064
    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to poison data based on an indication provided by a host device coupled with the memory devices. The indication may include which one or more bits to poison (invert) at which stages of performing write or read operations. In some embodiments, the memory device may invert one or more bits according to the indication and then correct one or more errors associated with inverting the one or more bit to verify its on-die ECC functionality. In some embodiments, the memory device may provide the host device with poisoned data including one or more bits inverted according to the indication such that the host device may test system-level ECC functionality using the poisoned data.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: December 20, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Joshua E. Alzheimer, Randall J. Rooney
  • Patent number: 11532356
    Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: December 20, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Amit S. Sharma, John Paul Strachan, Catherine Graves, Suhas Kumar, Craig Warner, Martin Foltin
  • Patent number: 11528094
    Abstract: An embodiment of the present disclosure contemplates a data sending and receiving method and apparatus. A first FEC unit of a sending device sends, by using a first channel, a first data stream on which first FEC encoding has been performed; a second FEC unit of the sending device sends, by using a second channel, a second data stream on which second FEC encoding has been performed; and the sending device performs interleaving on the first data stream and the second data stream, to obtain an output data stream, and sends the output data stream to a receiving device and error correction capability of a receiving device could be improved. In addition, in the present disclosure, an operation of writing by row and reading by column does not need to be performed. Therefore, no delay is generated.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: December 13, 2022
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Wenbin Yang, Tongtong Wang, Xinyuan Wang
  • Patent number: 11527298
    Abstract: An on-chip memory diagnostic (OCMD) circuit may instruct a set of built-in self-test (BIST) engines to execute BIST on memories associated with the set of BIST engines. Next, results of executing BIST on the memories may be received from the set of BIST engines. A set of memory failures may then be identified in the memories based on the results. Next, one or more BIST engines in the set of BIST engines may be instructed to collect diagnostic data for each memory failure. A set of diagnostic data may then be received for the set of memory failures. Next, the set of diagnostic data may be stored in an on-chip data container. The set of diagnostic data may then be provided via a communication channel.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: December 13, 2022
    Assignee: Synopsys, Inc.
    Inventors: Karen Darbinyan, Tatevik Melkumyan, Yervant Zorian
  • Patent number: 11527299
    Abstract: A method, apparatus, non-transitory computer readable medium, and system for using an error correction code in a memory device with a neural network are described. Embodiments of the method, apparatus, non-transitory computer readable medium, and system may receive a signal from a physical channel, wherein the signal is based on a modulated symbol representing information bits encoded using an error correction coding scheme, extract features from the signal using a feature extractor trained using probability data collected from the physical channel, and decode the information bits with a neural network decoder taking the extracted features as input.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: December 13, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Amit Berman, Evgeny Blaichman, Ron Golan
  • Patent number: 11522563
    Abstract: A storage circuit is configured to store multiple vectors associated with variable and check nodes of an iterative decoding operation. As part of the iterative decoding operation, a processor circuit is configured to retrieve, from the storage circuit, an intermediate value vector, a first estimation vector, a second estimation vector, and a sign vector, and determine an absolute value of the intermediate value vector. The processor circuit is also configured, using the retrieved vectors, to generate updated values for the first and second estimation vectors as part of determining a bit estimate for a check node included in the iterative decoding operation.
    Type: Grant
    Filed: October 13, 2021
    Date of Patent: December 6, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Alexander Bazarsky, Ran Zamir, Eran Sharon
  • Patent number: 11515890
    Abstract: Technologies for applying a redundancy encoding scheme to segmented portions of a data block include an endpoint computing device communicatively coupled to a destination computing device. The endpoint computing device is configured to divide a block of data into a plurality of data segments as a function of a transmit window size and a redundancy encoding scheme, and generate redundant data usable to reconstruct each of the plurality of data segments. The endpoint computing device is additionally configured to format a series of network packets that each includes a data segment of the plurality of data segments and generated redundant data for at least one other data segment of the plurality of data segments. Further, the endpoint computing device is configured to transport each of the series of network packets to a destination computing device. Other embodiments are described herein.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: November 29, 2022
    Assignee: Intel Corporation
    Inventors: Patrick Connor, Kapil Sood, Scott Dubal, Andrew Herdrich, James Hearn
  • Patent number: 11513891
    Abstract: Various implementations described herein relate to systems and methods for providing data protection and recovery for drive failures, including receiving, by a storage device, a write request from a host operatively coupled to a storage device, and determining, by the storage device instead of the host, an XOR result by performing an XOR operation of new data and existing data. The new data is received from the host. The existing data is stored in the non-volatile storage.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: November 29, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Yaron Klein, Krishna R. Malakapalli, Jeremy Werner
  • Patent number: 11507460
    Abstract: A memory controller for controlling a memory operation of a memory device includes: an error correction code (ECC) circuit configured to detect an error of first read data read from the memory device and correct the error; an error type detection logic configured to write first write data to the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparing, and output information about an error type identified by the error bit; and a data patterning logic configured to change a bit pattern of input data to reduce an error of the second read data based on the information about the error type.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: November 22, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeongho Lee, Youngsik Kim, Seungyou Baek, Eunchu Oh, Youngkwang Yoo, Younggeun Lee