Patents Examined by Kyle Vallecillo
  • Patent number: 11150842
    Abstract: A dynamic memory controller and method for use therewith are provided. In one example, a memory controller comprises dynamically-programmable components that can be used to configure the memory controller to be used with any number of selected host and/or memory types, as well as to enable the memory controller with different error detection/correction functionality.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: October 19, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Sesibhushana Rao Bommana, Mukesh Panda
  • Patent number: 11144390
    Abstract: An exemplary method for reading data stored in a flash memory includes: selecting an initial gate voltage combination from a plurality of predetermined gate voltage combination options; controlling a plurality of memory units in the flash memory according to the initial gate voltage combination, and reading a plurality of bit sequences; performing a codeword error correction upon the plurality of bit sequences, and determining if the codeword error correction successful; if the codeword error correction is not successful, determining an electric charge distribution parameter; determining a target gate voltage combination corresponding to the electric charge distribution parameter by using a look-up table; and controlling the plurality of memory units to read a plurality of updated bit sequences according to the target gate voltage combination.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: October 12, 2021
    Assignee: Silicon Motion, Inc.
    Inventor: Tsung-Chieh Yang
  • Patent number: 11144393
    Abstract: A memory controller for controlling a memory operation of a memory device includes: an error correction code (ECC) circuit configured to detect an error of first read data read from the memory device and correct the error; an error type detection logic configured to write first write data to the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparing, and output information about an error type identified by the error bit; and a data patterning logic configured to change a bit pattern of input data to reduce an error of the second read data based on the information about the error type.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: October 12, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeongho Lee, Youngsik Kim, Seungyou Baek, Eunchu Oh, Youngkwang Yoo, Younggeun Lee
  • Patent number: 11146287
    Abstract: An apparatus and method for optimizing a physical layer parameter is provided. According to one embodiment, an apparatus includes a first neural network configured to receive a transmission environment and a block error rate (BLER) and generate a value of a physical layer parameter; a second neural network configured to receive the transmission environment and the BLER and generate a signal to noise ratio (SNR) value; and a processor connected to the first neural network and the second neural network and configured to receive the transmission environment, the generated physical layer parameter, and the generated SNR, and to generate the BLER.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: October 12, 2021
    Inventors: Kee-Bong Song, Ahmed A. Abotabl, Jung Hyun Bae
  • Patent number: 11146288
    Abstract: Technologies for applying a redundancy encoding scheme to segmented portions of a data block include an endpoint computing device communicatively coupled to a destination computing device. The endpoint computing device is configured to divide a block of data into a plurality of data segments as a function of a transmit window size and a redundancy encoding scheme, and generate redundant data usable to reconstruct each of the plurality of data segments. The endpoint computing device is additionally configured to format a series of network packets that each includes a data segment of the plurality of data segments and generated redundant data for at least one other data segment of the plurality of data segments. Further, the endpoint computing device is configured to transport each of the series of network packets to a destination computing device. Other embodiments are described herein.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: October 12, 2021
    Assignee: Intel Corporation
    Inventors: Patrick Connor, Kapil Sood, Scott Dubal, Andrew Herdrich, James Hearn
  • Patent number: 11139918
    Abstract: Various embodiments provide an interleaving method, to improve error correction performance of a polar code. In these embodiments, a first bit sequence is obtained. The first bit sequence includes L number of bits, and L is a positive integer. The L number of bits are then written into an interleaving matrix according to a preset write rule. The interleaving matrix includes C rows and R number of columns. C and R are positive integers. The L number of bits can be read from the interleaving matrix according to a preset read rule to obtain a second bit sequence. The second bit sequence includes L number of bits; and sending the second bit sequence.
    Type: Grant
    Filed: March 8, 2020
    Date of Patent: October 5, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yue Zhou, Guijie Wang, Rong Li, Yinggang Du
  • Patent number: 11125819
    Abstract: A device includes a comparator, a reference signal node, a plurality of test signal nodes, and control logic. The reference signal node receives a reference signal. The reference signal node is coupled to a first input of the comparator. Each of the plurality of test signal nodes receives a corresponding test signal. The control logic is configured to initiate a comparison of each test signal to the reference signal via the comparator.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: September 21, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Shigekazu Yamada
  • Patent number: 11128320
    Abstract: This application relates to the communications field, and discloses an encoding method, a decoding method, an encoding apparatus, and a decoding apparatus. The encoding method includes: receiving a data bitstream; performing forward error correction FEC encoding on the data bitstream to obtain X Reed-Solomon RS outer codes, where each of the X RS outer codes includes N1 symbols, K1 of the N1 symbols are payload symbols; and performing FEC encoding on the X RS outer codes to obtain Y RS inner codes, where each of the Y RS inner codes includes N2 symbols, K2 of the N2 symbols are payload symbols. According to this application, error correction performance of FEC decoding can be improved.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: September 21, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yuchun Lu, Liang Li, Lin Ma
  • Patent number: 11128400
    Abstract: A bit assignment estimating device that accurately estimates bit assignment of a payload with fewer division patterns is provided. The bit assignment estimating device: divides a payload of received communication data to generate a plurality of blocks; estimates bit assignment of a block to be a certain value type; concatenates a block, which is adjacent to either of a block or a concatenation block which is estimated to be the continuous value type at a higher-order bit side, to the block or the concatenation block which is estimated to be the continuous value type when the block adjacent is estimated to be the status value type or the continuous value type; estimates whether the concatenation block is the continuous value type or not; and separates an immediately-close-concatenated block from a corresponding concatenation block when the concatenation block is estimated not to be the continuous value type.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: September 21, 2021
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Takuma Koyama, Masashi Tanaka, Yasushi Okano
  • Patent number: 11113213
    Abstract: An interface of a memory sub-system can determine that a particular write command received from a host has a same address as a subsequently received write command from the host. The interface can delete the particular write command if it is still in the interface or send a signal to delete the particular write command if the write command has already been provided from the interface.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: September 7, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Yue Chan
  • Patent number: 11115061
    Abstract: A datum is written to a memory, by splitting a binary word, representative of the datum and an error correcting or detecting code, into a first part and a second part. The first part is written at a logical address in a first memory circuit. The second part is written at the logical address in a second memory circuit. The error correcting or detecting code is dependent on both the datum and the logical address.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: September 7, 2021
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Alps) SAS
    Inventors: Fabrice Romain, Mathieu Lisart, Patrick Arnould
  • Patent number: 11115058
    Abstract: In a coding device (20), a first coding unit (21) generates a parity of an RS code by coding, based on the RS code, each first data sequence existing in a direction different from a row direction of input data, and generates coded data by attaching the parity of the RS code to each first data sequence, thereby consequently expanding a matrix. A second coding unit (22) generates a parity of a BCH code and a parity of an LDPC code by coding, based on the BCH code and the LDPC code, each second data sequence existing in a row direction of the coded data, and generates a plurality of DVB-S2 frames (13) including, per DVB-S2 frame (13), one data sequence existing in the row direction of the coded data, the corresponding parity of the BCH code, and the corresponding parity of the LDPC code.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: September 7, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hideo Yoshida, Shinya Hirakuri, Toshiyuki Kuze
  • Patent number: 11106535
    Abstract: An error correction circuit includes an error correction code (ECC) encoder and an ECC decoder. The ECC encoder generates, based on a main data, a parity data using an ECC represented by a generation matrix and stores a codeword including the main data and the parity data in a target page. The ECC decoder reads the codeword from the target page as a read codeword based on an externally provided address to generate different syndromes based on the read codeword and a parity check matrix which is based on the ECC, and applies the different syndromes to the main data in the read codeword to correct a single bit error when the single bit error exists in the main data or to correct two bit errors when the two bit errors occur in adjacent two memory cells in the target page.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: August 31, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sunghye Cho, Kijun Lee, Yeonggeol Song, Sungrae Kim, Chanki Kim, Myungkyu Lee, Sanguhn Cha
  • Patent number: 11101820
    Abstract: A memory control method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: sending a first read command sequence which indicates a reading of a first physical unit by using a first read voltage level to obtain first data; decoding the first data; sending a second read command sequence which indicates a reading of the first physical unit by using a second read voltage level to obtain second data; decoding the second data with assistance information to improve a decoding success rate of the second data if the second read voltage level meets a first condition or the second data meets a second condition; and decoding the second data without the assistance information if the second read voltage level does not meet the first condition and the second data does not meet the second condition.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: August 24, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Shih-Jia Zeng, Yu-Cheng Hsu, Yu-Siang Yang
  • Patent number: 11095314
    Abstract: Devices and methods described herein decode a sequence of coded symbols by guessing noise. In various embodiments, noise sequences are ordered, either during system initialization or on a periodic basis. Then, determining a codeword includes iteratively guessing a new noise sequence, removing its effect from received data symbols (e.g. by subtracting or using some other method of operational inversion), and checking whether the resulting data are a codeword using a codebook membership function. This process is deterministic, has bounded complexity, asymptotically achieves channel capacity as in convolutional codes, but has the decoding speed of a block code. In some embodiments, the decoder tests a bounded number of noise sequences, abandoning the search and declaring an erasure after these sequences are exhausted. Abandonment decoding nevertheless approximates maximum likelihood decoding within a tolerable bound and achieves channel capacity when the abandonment threshold is chosen appropriately.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: August 17, 2021
    Assignees: Massachusetts Institute of Technology, National University of Ireland Maynooth
    Inventors: Muriel Medard, Kenneth R. Duffy
  • Patent number: 11092647
    Abstract: A programmable integrated circuit may include logic, signal select hardware, programmable signal analysis hardware, an embedded microcontroller, and a hardware interface. The logic performs one or more functions and outputs a plurality of signals. The signal select hardware selects one or more of the signals output from the logic. The programmable signal analysis hardware analyzes the selected signals to produce diagnostic data. The embedded microcontroller receives the diagnostic data from the programmable signal analysis hardware and may reconfigure the logic based on the diagnostic data. The hardware interface connects the programmable signal analysis hardware and the embedded microcontroller to transport the diagnostic data.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: August 17, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: John E. Tilleman, Peter David Maroni, Erin Hallinan
  • Patent number: 11081201
    Abstract: A parallel test device is provided. The parallel test device of the disclosure includes an I/O pad, a plurality of input buffers, and a plurality of output drivers. The I/O pad is configured to perform input/output operations in the parallel test device. The input buffers are configured to enable write data. The output drivers are configured to enable read data and output the read data to the I/O pad. A test signal corresponds to the data from an external device is transferred to the output drivers through the I/O pad in the parallel test device during a test mode.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: August 3, 2021
    Assignee: Winbond Electronics Corp.
    Inventor: Chan-Seok Park
  • Patent number: 11082065
    Abstract: The present technology relates to a data processing apparatus and a data processing method that are able to provide an LDPC code with a good error rate. An LDPC encoder performs coding by an LDPC code having a code length of 16200 bits and a code rate of 12/15. The LDPC code includes an information bit and a parity bit, and a parity check matrix H is configured with an information matrix portion corresponding to the information bit of the LDPC code and a parity matrix portion corresponding to the parity bit. An information matrix portion of the parity check matrix H is represented by a parity check matrix initial value table representing a position of an element of 1 in the information matrix portion at an interval of 360 columns. The present technology may be applied to a case of performing an LDPC coding and an LDPC decoding.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: August 3, 2021
    Assignee: SATURN LICENSING LLC
    Inventors: Yuji Shinohara, Makiko Yamamoto
  • Patent number: 11080136
    Abstract: A computer-implemented method for dropped write error detection is proposed. In the method, a read request for a stride stored in an array of storage drives is received. The stride includes segments of a data and a first parity associated with the data spreading across the storage drives in the array of the storage drives. In response to the read request being a predefined sequential read request and a state of the stride being a first state, a parity check is performed on the stride. The first state indicates that no parity check has been performed after the data is written into the array of storage drives. The state of the stride is changed to a second state, and the second state is different with the first state.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: August 3, 2021
    Assignee: International Business Machines Corporation
    Inventors: Gang Lyu, Jun Gu, Hong Zhou
  • Patent number: 11082067
    Abstract: Embodiments described herein provide a code generation mechanism (FIG. 3, 301) in a Polar encoder (FIG. 2, 204) to determine a bit type (FIG. 3, 312) corresponding to each coded bit in the Polar code before sending the data bits for encoding (FIG. 3, 303). For example, each bit in the Polar code is determined to have a bit type of a frozen bit, parity bit, an information bit, or a cyclic redundancy check (CRC) bit based at least on the respective reliability index of the bit from a pre-computed reliability index lookup table (FIG. 4A, 411). In this way, the bit type determination can be completed in one loop by iterating the list of entries in the pre-computed reliability index lookup table.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: August 3, 2021
    Assignee: XILINX, INC.
    Inventors: Ming Ruan, Gordon I. Old, Richard L. Walke, Zahid Khan