Patents Examined by Kyle Vallecillo
  • Patent number: 10819466
    Abstract: A system includes a processor configured to determine that transmission data indicates that first data was transmitted via a digital radio channel and that reception data indicates that second data was received via the digital radio channel. The first data is transmitted concurrently with transmission of an analog signal. The processor is configured to detect an error in transmission of the first data based on a comparison of adjacent portions of the first data to non-adjacent portions of the second data. The processor is configured to, in response to detecting the error, initiate display of a default image concurrently with output of an audio signal that is based on the analog signal and to initiate retransmission of the first data to cause second particular data to be output subsequent to the output of the default image. The second particular data corresponds to the retransmitted first data.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: October 27, 2020
    Assignee: iHeartMedia Management Services, Inc.
    Inventors: Jeff Littlejohn, Abineshraj Rajagopal, Amit Deshpande, Alan W. Jurison, Charles E. Kirkendall, III
  • Patent number: 10817370
    Abstract: A self-correcting memory device (SCMD) includes a non-destructive memory array that includes memory cells arranged in rows and columns that includes a storage section, a comparison section, a comparing element, a selective write unit and a row decoder. The storage section stores a first copy, a second copy and a third copy of a data item in physically separated columns. The comparison section temporarily stores the first copy in a first row and the second copy in a second row. The comparing element compares between bits of the first and second rows and provides at least one per bit change indication. The selective write unit receives at least one per bit change indication and fetches from the third copy a correct value for each bit having a positive bit change indication. The row decoder concurrently writes each correct value back to its bit location in the first and second copies.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: October 27, 2020
    Assignee: GSI Technology Inc.
    Inventor: Avidan Akerib
  • Patent number: 10818369
    Abstract: A semiconductor circuit of the disclosure includes: a sequential circuit unit including a plurality of logic circuit units that include respective flip flops and respective non-volatile storage elements, the sequential circuit unit performing, in a first term, store operation in which the storage elements in the plurality of the logic circuit units store respective voltage states in the plurality of the logic circuit units, and shift operation in which the flip flops in the plurality of the logic circuit units operate as a shift register; and a first memory that stores, in the first term, first data or second data, the first data being outputted from the shift register by the shift operation, and the second data corresponding to the first data.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: October 27, 2020
    Assignee: Sony Corporation
    Inventor: Keizo Hiraga
  • Patent number: 10812227
    Abstract: Modern mobile communication systems transfer data by error protection measures including the use of a forward error correction code for the channel coding and a HARQ (hybrid automatic repeat request) system for the repeated transfer of incorrect transport blocks in response to the error protection mechanisms failing. When a turbo code is used as an error protection code, two decoders work on the decoding of the turbo code. Disclosed is an expanded HARQ system wherein the receiving side determines which of the decoders was more greatly challenged in the decoding of the turbo code and reports this to the transmitting side. Instead of uniformly providing more redundancy data to both decoders, more redundancy data are targetedly provided to the more greatly challenged decoder in the expanded HARQ process than in the case of the repetition operation according to the typical HARQ process reducing the latency of the data transfer.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: October 20, 2020
    Assignee: VOLKSWAGEN AKTIENGESELLSCHAFT
    Inventor: Thorsten Hehn
  • Patent number: 10812109
    Abstract: A circuit arrangement for determining in parallel of at least two byte error position signals for identifying at least one byte error in a binary sequence comprising a plurality of bytes, wherein the binary sequence in the error-free case is a code word of an error code, the circuit arrangement is configured such that each of the at least two byte error position signals is determinable using components of an error syndrome of the error code such that the components indicate whether or not a byte of the binary sequence that is associated with the byte error position signal is erroneous.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: October 20, 2020
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kern, Christian Badack, Michael Goessel
  • Patent number: 10811115
    Abstract: A test method for testing a built-in memory in a computer device includes the following operations. The built-in memory is tested by a test function of a basic input/output system (BIOS) in the computer device to create a data file. An analysis application is performed by a test device to analyze the data file. According to analyzing the data file, an abnormal memory chip is determined whether to exist in the built-in memory. The data file includes test data of memory chips in the built-in memory.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: October 20, 2020
    Assignees: Inventec (Pudong) Technology Corporation, INVENTEC CORPORATION
    Inventors: Tzu-Pin Wang, Kuo-Hsin Hsu, I-Ting Liu, Che-Sheng Cheng
  • Patent number: 10812111
    Abstract: A semiconductor apparatus includes a storage unit, an ECC decoder, and a selection unit. The storage unit stores data. The ECC decoder can detect and correct an error of a predetermined number of bits in data outputted from the storage unit, and can detect an error equal to or larger than bits larger than the predetermined number of bits in the data. The selection unit selects and outputs one of the data outputted from the ECC decoder and a preset fixed value, in accordance with a detection signal indicating whether or not the error equal to or larger than the bits larger than the predetermined number of bits is detected by the ECC decoder.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: October 20, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Keisyun Lin
  • Patent number: 10812222
    Abstract: The present technique relates to a transmission apparatus, a transmission method, a reception apparatus, and a reception method that can ensure favorable communication quality in data transmission using an LDPC code. LDPC coding is performed based on a check matrix of an LDPC code with a code length N of 69120 bits and a code rate r of 7/16 or 8/16. The LDPC code includes information bits and parity bits, and the check matrix includes an information matrix corresponding to the information bits and a parity matrix corresponding to the parity bits. The information matrix is represented by a check matrix initial value table. The check matrix initial value table is a table indicating positions of elements of 1 in the information matrix on the basis of 360 columns and is a predetermined table. The present technique can be applied to, for example, data transmission using the LDPC code.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: October 20, 2020
    Assignee: SONY CORPORATION
    Inventors: Yuji Shinohara, Makiko Yamamoto
  • Patent number: 10810495
    Abstract: A method is disclosed comprising encoding a message into blocks, determining a collection of DNA symbols for each of the blocks from the encoded message, performing a second encoding of the determined collection of DNA symbols from the encoded message, detecting a presence of errors in the second encoding and establishing an authentication of each block and further using zero-knowledge protocol to securely authenticate the message without disclosing the actual message.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: October 20, 2020
    Assignee: UNIVERSITY OF WYOMING
    Inventors: Don Roth, Siguna Mueller, Farhad Jafari
  • Patent number: 10803971
    Abstract: A device for supporting a test mode for memory testing according to an example embodiment of the inventive concepts may include a memory configured to receive and store writing data and output reading data from the stored writing data; an error correction code (ECC) engine configured to generate the writing data by encoding input data and to generate output data by correcting error bits of N bits or less included in receiving data when N is a positive integer; and an error insertion circuit configured to provide the reading data to the ECC engine as the receiving data in a normal mode and to provide data obtained by inverting at least one bit of less than N bits of the reading data to the ECC engine as the receiving data in the test mode.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: October 13, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Suk-soo Pyo, Hyun-taek Jung, Tae-joong Song
  • Patent number: 10805044
    Abstract: Devices, computer-readable media, and methods for selecting a type of packet loss protection for a network-based communication based upon a latency estimate are disclosed. For example, a processing system including at least one processor may obtain a latency estimate for a network-based communication, determine whether the latency estimate exceeds a latency threshold for selecting a type of packet loss protection, and select, the type of packet loss protection for the network-based communication from among a first type of packet loss protection and a second type of packet loss protection based upon the determining. When the latency estimate is determined to not exceed the latency threshold, the first type of packet loss protection is selected. When the latency estimate is determined to exceed the latency threshold, the second type of packet loss protection is selected.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: October 13, 2020
    Assignee: AT&T Intellectual Property I, L.P.
    Inventors: Zhengye Liu, Xidong Wu, Jin Wang, Bo Han
  • Patent number: 10795764
    Abstract: A data chip that may pollute data is disclosed. The data chip may include a data array, read circuitry to read raw data from the data array, and a buffer to store the raw data. Using a pollution pattern stored in a mask register, a data pollution engine may pollute the raw data. Transmission circuitry may then transmit the polluted data.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: October 6, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dimin Niu, Mu-Tien Chang, Hongzhong Zheng, Hyun-Joong Kim, Won-Hyung Song, Jangseok Choi
  • Patent number: 10797828
    Abstract: An embodiment of the present invention discloses a data sending and receiving method. A first FEC unit of a sending device sends, by using a first channel, a first data stream on which first FEC encoding has been performed; a second FEC unit of the sending device sends, by using a second channel, a second data stream on which second FEC encoding has been performed; and the sending device performs interleaving on the first data stream and the second data stream, to obtain an output data stream, and sends the output data stream to a receiving device and error correction capability of a receiving device could be improved. In addition, in the present invention, an operation of writing by row and reading by column does not need to be performed. Therefore, no delay is generated.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: October 6, 2020
    Assignee: HUAWEI TECHNOLOGIES CO.,LTD.
    Inventors: Wenbin Yang, Tongtong Wang, Xinyuan Wang
  • Patent number: 10790853
    Abstract: Concepts and schemes pertaining to quasi-cyclic-low-density parity-check (QC-LDPC) coding are described. A processor of an apparatus may generate a QC-LDPC code having a plurality of codebooks embedded therein. The processor may select a codebook from the plurality of codebooks. The processor may also encode data using the selected codebook. Alternatively or additionally, the processor may generate the QC-LDPC code including at least one quasi-row orthogonal layer. Alternatively or additionally, the processor may generate the QC-LDPC code including a base matrix a portion of which forming a kernel matrix that corresponds to a code rate of at least a threshold value.
    Type: Grant
    Filed: November 25, 2018
    Date of Patent: September 29, 2020
    Assignee: MEDIATEK INC.
    Inventors: Mao-Ching Chiu, Chong-You Lee, Cheng-Yi Hsu, Timothy Perrin Fisher-Jeffes, Yen-Shuo Chang, Wei-Jen Chen, Ju-Ya Chen
  • Patent number: 10778255
    Abstract: A network device polar encodes data to obtain a first encoded bit sequence, wherein the first encoded bit sequence comprises: bits in even number locations in the first encoded bit sequence and bits in odd number locations in the first encoded bit sequence; then the device interleaves the first encoded bit sequence to obtain an interleaved bit sequence; finally, the device rate matches the interleaved bit sequence and outputs the bit sequence after rate matched, wherein bits in even number locations of the interleaved bit sequence are from the bits in even number locations of the first encoded bit sequence, bits in odd number locations of the interleaved bit sequence are from the bits in odd number locations of the first encoded bit sequence.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: September 15, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Hui Shen, Bin Li, Jun Chen
  • Patent number: 10776193
    Abstract: Technologies are disclosed for identifying and remediating correctable hardware errors. A firmware can detect a system management interrupt (“SMI”) generated by a hardware device responsive to the occurrence of a correctable error. Once the firmware has identified the device that generated the SMI, the firmware can determine whether an earliest recorded error generated by the identified device is longer ago than a threshold amount of time. If the earliest recorded error generated by the device is not longer ago than the threshold amount of time, the firmware can increment an error count for the device. The firmware can also determine whether the error count for the device exceeds a threshold. If the error count for the device exceeds the threshold, the firmware can generate an error notification for the device. The firmware can also implement a remedial action policy for the device.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: September 15, 2020
    Assignee: AMERICAN MEGATRENDS INTERNATIONAL, LLC
    Inventors: Manickavasakam Karpagavinayagam, Manish Jha, Altaf Hussain, Harikrishna Doppalapudi, Purandhar Nallagatla
  • Patent number: 10778252
    Abstract: A solution is disclosed for using low-density parity check codes in connection with a retransmission scheme. A first apparatus encodes a data bit set by using a first parity check matrix in a low-density parity check encoder. The first apparatus transmits the encoded data bit set and some parity bits of the set to a second apparatus in a message, and determines that the second apparatus was not capable of decoding the data bit set. The first apparatus modifies the first parity check matrix by using an overlapping matrix where overlapping elements of the first parity check matrix and the overlapping matrix are combined into a second parity check matrix. The first apparatus encodes the data bit set by using the second parity check matrix to provide a second parity bit set, and transmits at least some parity bits of the second parity bit set to the second apparatus.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: September 15, 2020
    Assignee: Nokia Technologies Oy
    Inventor: Edgars Curkste
  • Patent number: 10767998
    Abstract: Information communication circuitry, including a first integrated circuit for coupling to a second integrated circuit in a package on package configuration. The first integrated circuit comprises processing circuitry for communicating information bits, and the information bits comprise data bits and error correction bits, where the error correction bits are for indicating whether data bits are received correctly. The second integrated circuit comprises a memory for receiving and storing at least some of the information bits. The information communication circuitry also includes interfacing circuitry for selectively communicating, along a number of conductors, between the package on package configuration. In a first instance, the interfacing circuitry selectively communicates only data bits along the number of conductors.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: September 8, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rahul Gulati, Aishwarya Dubey, Nainala Vyagrheswarudu, Vasant Easwaran, Prashant Dinkar Karandikar, Mihir Mody
  • Patent number: 10772153
    Abstract: Methods and apparatus for two-stage ACK/DTX detection. In an embodiment, a method includes determining a first stage DTX value from bit-domain correlation values, and determining a second stage DTX value from symbol domain correlation values generated from candidate ACK bits. The method also includes determining a DTX decision based on the first stage DTX value and the second stage DTX value.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: September 8, 2020
    Assignee: CAVIUM, LLC.
    Inventors: Yuanbin Guo, Hong Jik Kim
  • Patent number: 10771189
    Abstract: Systems and devices can include a first port of a first device coupled to a second port of a second device across a multi-lane link. The first port can augment a data block with error correcting code by distributing error correcting code evenly across each lane of the data block, wherein each lane of the data block includes a same number of error correcting code. The first port can transmit the data block with the per-lane error correcting code to the second port across the multi-lane link. The second port can determine error correcting code based on the error correcting code bits received in the data block, and perform error correction on the symbols of the data block based on the error correcting code received.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: September 8, 2020
    Assignee: Intel Corporation
    Inventor: Debendra Das Sharma