Abstract: An apparatus includes an error read flow component resident on a memory sub-system. The error read flow component can cause performance of a plurality of read recovery operations on a group of memory cells that are programmed or read together, or both. The error read flow component can determine whether a particular read recovery operation invoking the group of memory cells was successful. The error read flow component can further cause a counter corresponding to each of the plurality of read recovery operations to be incremented in response to a determination that the particular read recovery operation invoking the group of memory cells was successful.

Abstract: An embodiment of the present disclosure contemplates a data sending and receiving method and apparatus. A first FEC unit of a sending device sends, by using a first channel, a first data stream on which first FEC encoding has been performed; a second FEC unit of the sending device sends, by using a second channel, a second data stream on which second FEC encoding has been performed; and the sending device performs interleaving on the first data stream and the second data stream, to obtain an output data stream, and sends the output data stream to a receiving device and error correction capability of a receiving device could be improved. In addition, in the present disclosure, an operation of writing by row and reading by column does not need to be performed. Therefore, no delay is generated.

Abstract: An apparatus is provided, comprising a plurality of memory devices and a buffering device that permits memory devices with a variety of physical dimensions and memory formats to be used in an industry-standard memory module format. The buffering device includes memory interface circuitry and at least one first-in first-out (FIFO) or multiplexer circuit. The apparatus further comprises a parallel bus connecting the buffering device to the plurality of memory devices. The parallel bus includes a plurality of independent control lines, each coupling the memory interface circuitry to a corresponding subset of a plurality of first subsets of the plurality of memory devices. The parallel bus further includes a plurality of independent data channels, each coupling the at least one FIFO circuit or multiplexer circuit to a corresponding subset of a plurality of second subsets of the plurality of memory devices.

Abstract: A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits to be transmitted to a receiver in a current frame; a repeater configured to repeat, in the LDPC codeword, at least some bits of the LDPC codeword in the LDPC codeword so that the repeated bits are to be transmitted in the current frame; a puncturer configured to puncture some of the parity bits; and an additional parity generator configured to select at least some bits of the LDPC codeword including the repeated bits, and generate additional parity bits to be transmitted in a previous frame of the current frame.

Abstract: Devices and methods described herein decode a sequence of coded symbols by guessing noise. In various embodiments, noise sequences are ordered, either during system initialization or on a periodic basis. Then, determining a codeword includes iteratively guessing a new noise sequence, removing its effect from received data symbols (e.g. by subtracting or using some other method of operational inversion), and checking whether the resulting data are a codeword using a codebook membership function. This process is deterministic, has bounded complexity, asymptotically achieves channel capacity as in convolutional codes, but has the decoding speed of a block code. In some embodiments, the decoder tests a bounded number of noise sequences, abandoning the search and declaring an erasure after these sequences are exhausted. Abandonment decoding nevertheless approximates maximum likelihood decoding within a tolerable bound and achieves channel capacity when the abandonment threshold is chosen appropriately.

Abstract: Disclosed is a quantum computing system including a first quantum chip including first physical qubits, a second quantum chip including second physical qubits, and a management device. The management device includes a physical qubit layer that manages physical qubit mapping including information about physical channels between first and second physical qubits, an abstraction qubit layer that manages abstraction qubit mapping including information about abstraction qubits and abstraction channels between the abstraction qubits based on the physical qubit mapping, a logical qubit layer that divides the abstraction qubits into logical qubits and to manage logical qubit mapping including information about logical channels between the logical qubits, based on the abstraction qubit mapping, and an application qubit layer that allocates at least one logical qubit corresponding to a qubit request received from a quantum application program based on the logical qubit mapping.

Abstract: A communications system, a method of operating a communications system, and a method of operating a communications device are provided.

Abstract: Separate inter-die connectors for data and error correction information and related apparatuses, methods, and computing systems are disclosed. An apparatus including a master die, a target die, inter-die data connectors, and inter-die error correction connectors. The target die includes data storage elements. The inter-die data connectors electrically couple the master die to the target die. The inter-die data connectors are configured to conduct write data bits from the master die to the target die. The write data bits are written to the data storage elements. The inter-die error correction connectors electrically couple the master die to the target die. The inter-die error correction connectors are configured to conduct error correction information corresponding to the write data bits from the master die to the target die. The target die includes error correction circuitry configured to generate new error correction information responsive to the write data bits received from the master die.

Abstract: A method includes determining a plurality of identifiers based on a data retrieval request. Integrity information is generated based on determining the plurality of identifiers. Stored integrity information corresponding to the data retrieval request is compared with the integrity information. When the stored integrity information compares unfavorably with the integrity information, corruption associated with the plurality of identifiers is determined.

Abstract: Apparatuses, systems, and methods for error correction. A memory array may be coupled to an error correction code (ECC) circuit along a read bus and a write bus. The ECC circuit includes a read portion and a write portion. As part of a mask write operation, read data and read parity may be read out along the read bus to the read portion of the ECC circuit and write data may be received along data terminals by the write portion of the ECC circuit. The write portion of the ECC circuit may generate amended write data based on the write data and the read data, and may generate amended parity based on the read parity and the amended write data. The amended write data and amended parity may be written back to the memory array along the write bus.

Abstract: A system and method for indicating, via a heralding signal, that an amplitude damping decay event has occurred within a quantum low-density parity-check (LDPC) code is disclosed. Logical information may be encoded into a superconducting qubit using one or more transmons, wherein a first level and a second level are encoded into a code space of the qubit, and at least one intermediate level outside of the code space characterizes an amplitude damping decay channel which is then used to herald an amplitude damping decay event. Dynamical decoupling pulse sequences may be used to drive such qubit structures and bias noise towards the amplitude damping decay channel. The one or more heralding signals within a lower-level code may then be used as input to a quantum LDPC code for decoding syndrome measurements with the knowledge of occurrences of amplitude damping decay as indicated via the one or more heralding signals.

Abstract: Various embodiments include an error correction code (ECC) system that provides protection against various errors in addition to data bit errors. In general, ECC codes protect against data bit errors, where one or more data bits in a data word contain the wrong value. The ECC code is based on the original data bits, such that a data bit error results in a data word that is inconsistent with the ECC code generated for and stored with the data word. The present embodiments generate ECC codes based on address information and/or sequencing information in addition to the data bits in the data word. As a result, the present embodiments detect bit errors in this address information and/or sequencing information. Such errors include write address decoding errors, read address decoding errors, write enable errors, and stale data errors.

Abstract: A memory device, a memory system, and a method of operating the same. The memory device includes a memory cell array including a plurality of memory cells and a write command determination unit (WCDU) that determines whether a write command input to the memory device is (to be) accompanied a masking signal. The WCDU produces a first control signal if the input write command is (to be) accompanied by a masking signal. A data masking unit combines a portion of read data read from the memory cell array with a corresponding portion of input write data corresponding to the write command and generates modulation data in response to the first control signal. An error correction code (ECC) engine generates parity of the modulation data.

Abstract: Methods, systems, and apparatuses include generating recovery likelihood metrics for undecodable segments in a stripe of data distributed across a redundant array of storage nodes. The recovery likelihood metrics are based on a determination of a likelihood of recovering the undecodable segment. The undecodable segments are ranked based on the recovery likelihood metrics. The undecodable segments are recovered in an order based on the ranking starting with the undecodable segment with the highest likelihood of recovery.

Abstract: Disclosed is a nonvolatile memory device, which includes a memory cell array including cell strings, a row decoder connected with a ground selection transistor of each of the cell strings through a ground selection line, connected with memory cells of each of the cell strings through word lines, and connected with a string selection transistor of each of the cell strings through a string selection line, and a page buffer connected with the cell strings through bit lines. In a first period of a check operation, the page buffer applies a first bias voltage to the bit lines, and the row decoder applies a turn-off voltage to the ground selection line, a turn-on voltage to the string selection line, and a first check voltage to the word lines. In a second period of the check operation, the page buffer senses first changes of voltages of the bit lines.

Abstract: A broadcast signal reception method, according to one embodiment of the present invention, may include receiving the broadcast signal including broadcast data and physical layer signaling information, where the physical layer signaling information includes frequency interleaver information for indicating whether a frequency interleaver is applied to the broadcast data, performing frequency deinterleaving on the broadcast data selectively based on the frequency interleaver information, convolutionally deinterleaving the broadcast data, block deinterleaving the convolutionally deinterleaved broadcast data, and cell deinterleaving the block deinterleaved broadcast data using a memory, where the cell deinterleaving includes random writing the block deinterleaved broadcast data into the memory and linear reading the block deinterleaved broadcast data from the memory, and the random writing is performed based on a permutation sequence and the permutation sequence varies for every FEC block.

Abstract: A method and system for performing a duty cycle correction and quadrature error correction for a quarter-rate architecture TX/RX communication system, including correcting a duty cycle error between a first clock signal and a second clock signal, and correcting a quadrature error between a third clock signal and a fourth clock signal.

Abstract: A system and method for error correction for machine-readable symbols having data codewords, and having error correction (EC) codewords derived from the data codewords and redundantly indicating the location and data contents of the data codewords. The symbols use Reed-Solomon (RS) error correction to retrieve damaged codewords. RS error correction normally requires two EC codewords to identify both the location and data contents of a data codeword. The present system and method perform optical contrast analysis on the codewords, identifying those codewords with the lowest contrast levels. Codewords with the lowest contrast levels are flagged as optically ambiguous, thereby marking, in the EC equations, the locations of the codewords most like to be in error. As a result, only a single EC codeword is required to retrieve the data for a flagged data codeword.

Abstract: Read parameter estimation techniques are provided that obtain information from multiple read operations to customize read parameters for data recovery. One method comprises performing the following steps, in response to a decoding failure of a codeword of the memory: obtaining at least three read values of the codeword; calculating a signal counts metric value from the at least three reads; computing an optimal reference voltage offset from the signal counts metric and a correlation between optimal reference voltage offsets and a signal counts metric associated with the memory; determining a new center read reference voltage based on a current center reference voltage and the optimal reference voltage offset and performing at least one subsequent read of the codeword following the decoding failure utilizing the new center read reference voltage.

Abstract: Embodiments of methods of communications, communications devices, and redrivers are disclosed. In an embodiment, a method of communications involves enabling a Loss of Signal (LOS) detector and a Low Frequency Periodic Signaling (LFPS) detector connected to a communications channel, using a digital logic circuit, combining an output of the LOS detector and an output of the LFPS detector to generate a combined LFPS output, and outputting the combined LFPS output and the output of the LOS detector to control data communications through the communications channel.