Abstract: An emergency notification service is described that is delivered using an evolved multimedia broadcast-multicast service (eMBMS). An emergency notification is sent out to user equipment (UE) in affected areas. In response to receiving the emergency notification, the UE searches the appropriate emergency multicast service acquisition information for multiple potential types of available emergency content that is provided by the eMBMS system in the network and tunes to the eMBMS to receive the emergency content. In selected aspects, the transmitted information, including the notifications and content may be scrambled using the same cell ID for each of the cells transmitting the same content. This improves the quality of the transmitted signals allowing for more reliable receipt and decoding by the receiving UEs.

Abstract: The present invention relates to handover in a communications system, and more especially it relates cell change using Iu-interface dependent neighbor-cell lists, particularly in a Universal Mobile Telecommunications System, UMTS or WCDMA system.

Abstract: A power-on reset circuit includes a first resistor having one end connected to a power source node; a first capacitor connected to another end of the first resistor; a second resistor having one end connected to the power source node; a second capacitor connected to another end of the second resistor; a first inverter having a power source terminal connected to the other end of the first resistor and an input terminal connected to the other end of the second resistor; and a second inverter having a power source terminal connected to the other end of the first resistor, an input terminal connected to an output terminal of the first inverter, and an output terminal electrically connected to a reset signal output terminal.

Abstract: Integrated Circuits (ICs) comprising circuits configured to generate a power on reset (POR) pulse are disclosed. An IC comprises a power supply sense circuit configured to generate a sense signal in response to a transition of a power supply signal from a first level to a second level, and a pulse generation circuit coupled with the power supply sense circuit. The pulse generation circuit is configured to generate a power on reset (POR) pulse of a threshold duration based on the sense signal. The IC further includes a reset generation circuit coupled with the pulse generation circuit to receive the POR pulse. The reset generation circuit is configured to generate a reset pulse based on the POR signal and of at least one control signal, where the reset pulse is configured to be utilized to perform a reset of one or more elements of the integrated circuit.

Abstract: A cavo-atrial cannula for removing blood from the body while performing heart surgery has at least two set of openings, a removable obturator, a curved tip, and a bend. The cavo-atrial cannula has the first openings located adjacent to the curved tip and the second openings on the side, opposite the bend. The cavo-atrial cannula contains various markings to indicate the correct positioning of the cavo-atrial cannula. The cavo-atrial cannula is inserted into the superior vena cava or inferior vena cava. The tip of the cavo-atrial cannula can lie in either the right atrium or the vena cava opposite from the insertion point. Because of the location of the second openings at the bend, blood from the head and upper body traveling through the superior vena cava or from the lower body traveling through the inferior vena cava can enter the lumen of the cavo-atrial cannula, thereby preventing the dangerous build up of blood upstream of the insertion point of the device.

Abstract: A circuit that translates one voltage level to another voltage level. In one embodiment of the invention, an input buffer translates a 3 volt level to a 5 volt level. Such an input buffer facilitates communications between 3 volt I/Os and 5 volt core logic and memories. And while the input buffer is described as being ideal for communications between 3 volt I/Os and 5 volt core logic and memories of a gate array, the translator circuitry of the invention can be used in a wide variety of electronic devices where a chip operating on 5 volts must interface with a 3 volt system.