Abstract: A signal processing system includes a receiving terminal configured to receive a digital signal comprising a plurality of samples associated with a plurality of original sampling times, wherein the original sampling times have a period of T, and a compensation module coupled to the receiving terminal. The compensation module is configured to generate, based on the digital signal, a nominal phase shifted signal having a plurality of nominal phase shifted samples associated with a plurality of phase shifted sampling times, wherein the plurality of phase shifted sampling times correspond to fractional intervals of the original sampling times. The compensation module is further configured to generate a compensated signal based at least in part on the digital signal and the nominal phase shifted signal.

Abstract: An amplifier circuit comprises a main stage amplifier connected between a RF input and a RF output and at least one secondary stage amplifier, which is connected in parallel to the main stage amplifier between the RF input and the RF output. The secondary stage amplifier comprises an input bipolar transistor, whose collector terminal or emitter terminal is high frequency-coupled to the RF input. The secondary stage amplifier further comprises an output bipolar transistor, whose base terminal is high frequency-coupled to the base terminal of the input bipolar transistor and whose collector terminal or emitter terminal is high frequency-coupled to the RF output. The output bipolar transistor is further coupled to a supply voltage terminal.

Abstract: A system for compressed digital video bitstreams, in which an I-frame may precede a plurality of P-frames slices, wherein the system includes an encoder to encode the bits for each successive P-frame slice. The system also includes a decoder buffer, where the bits enter at a fixed rate and a decoder, which uses the extracted bits to decode each frame and display each frame. The delay is chosen at a fixed rate between 10 msec and 100 msec.

Abstract: A charge balancing modulation system for digitizing the output of a variable impedance sensor utilizes synchronous excitation of the input sensor and AC coupling of the analog input signal. The modulation system also implements correlated double sampling to provide low noise and highly accurate analog-to-digital conversions. In one embodiment, the modulation system includes an excitation source for providing a switched current to the input sensor and generating an input voltage step in response, and an integrator including an input capacitor, an amplifier and an accumulation capacitor. The input capacitor AC couples the analog input signal to the integrator. The integrator is controlled by switches operating in complementary state for enabling correlated double sampling operation or enabling data dependent charge accumulation operation. The modulation system generates an output data stream exhibiting a ones density proportional to the magnitude of the average input voltage step.

Abstract: A D/A converter is provided which is capable of avoiding an increase in occupied areas of the D/A converter on a board and of obtaining an output characteristic being excellent in linearity, which enables achievement of the D/A converter having a small integral-linearity error (INL) and a small differential-linearity error (DNL). The reference current composite blocks are cascaded between current controlling device groups and an output switch. At least one out of reference current composite blocks divides composite reference current amounts based on a predetermined weight and outputs them.

Abstract: A method for run-length encoding two or more data values, the method comprising: loading the data values into storage by forming a first data string, the data string comprising a plurality of data sub-strings and each data sub-string representing at least one of the data values; generating a second data string having a data sub-string corresponding to each data sub-string of the first data string, all the bits of each of the data sub-strings of the second data string having a first predetermined value if all the bits of the corresponding data sub-string of the first data string have a second predetermined value and having a third predetermined value if any of the bits of the corresponding data sub-string of the first data string has other than the second predetermined value; starting from a predetermined end of the second data string, counting the number of consecutive bits of the second data spring having the first predetermined value; and dividing the said number by the number of bits in each data sub-strin

Abstract: A method for correcting an analog signal to target levels is provided. Firstly, the analog signal is periodically sampled to obtain a plurality of sampled points. Then, levels of the sampled points are compared with a threshold value to find a set of sequentially sampled points including a head and a tail ones, each having a first comparing result with the threshold value, and the other intermediate ones, each having a second comparing result with the threshold value. Then, one of the set of sequentially sampled points, which has the second comparing result with the threshold value, is adjusted to one of the target levels. A device for correcting an analog signal to target levels is also provided.

Abstract: Each input binary digit of an input serial bit string having a referential word in a referential word time period is sampled N times to produce a plurality of over-sampled binary digits corresponding to a first group of sampling operations, a second group of sampling operations,--, an N-th group of sampling operations, and the over-sampled binary digits are divided to N divided bit strings corresponding to the N groups of sampling operations respectively. Because each divided bit string having the referential word is correctly sampled at high probability, a word start position of the referential word in each divided bit string is detected, one divided bit string correctly sampled at the highest probability is selected, and a string of words starting from the word start position is retrieved from the selected divided bit string and is output.

Abstract: A pipeline/subranging architecture is used to provide a circuit for analog to a digital conversion. A course analog to digital converter, a fine analog to digital to converter, combining logic circuitry and a digital to analog converter are used, together with a voltage to current converter and a current to voltage converter. A residual signal is formed as the difference between the input signal and an output signal of the coarse analog to digital conversion, the latter output signal having been converted to analog form by the analog to digital converter. The residual signal is then scaled appropriately and applied to the fine analog to digital converter. A final output signal is based on the output signals of the coarse digital to analog converter and the fine digital to analog converter.

Abstract: In a method and apparatus for digital-to-analog signal conversion, each of a plurality of first capacitors is charged during a first time period in accordance with an associated data bit of an input data byte. During a second time period that follows the first time period, the first capacitors are connected to a second capacitor for charge redistribution. During a third time period that follows the second time period, the second capacitor is connected to an operational amplifier to generate an analog output corresponding to the input data byte.

Abstract: A decision feedback equalizer includes a lookup table device. The lookup table device may include a shift register and memory, or may include multiple shift registers and memories. Near-end crosstalk may be reduced using a lookup table device. Echo in a bi-directional port circuit may also be reduced using a lookup table device.

Abstract: The present invention is a pipelined analog-to-digital converter (Pipelined ADC) for converting a first analog signal to a digital data. The converter comprises at least one first stage circuit, at least one second stage circuit, a third stage circuit, and a code adder. Each of the first stage circuits has a first converting rate for converting a first analog signal to at least one digital code and generating a second analog signal. The second stage circuits are serially connected after the first stage circuit. Each of the second stage circuits has a second converting rate which is higher than the first converting rate for converting the second analog signal to at least two digital codes and generating a third analog signal. The third stage circuit serially connected after the second stage circuits is used for converting the third analog signal to at least one digital code. The code adder is used for combining the digital codes to generate the digital data.

Abstract: A constant “R” network distributed amplifier formed in a multi-layer, low temperature co fired ceramic structure comprises multiple cascaded constant “R” networks for amplifying a signal applied thereto. Each one of the multiple cascaded constant “R” networks is formed in the ceramic structure and includes a plurality of ceramic layers each of which have a top and bottom planar surfaces which, when bonded together form the ceramic structure. A transmission line is formed on the top surfaces of each of the ceramic layers having a beginning end and a distal end and has a generally rectangular shape. The distal end of the transmission line formed on a lower ceramic layer is connected to the beginning end of the transmission line formed on the next adjacent upper ceramic layer by way of vias formed in the ceramic layers through which metal conductive material is formed there through.

Abstract: Digital-to-analog converter architecture guarantees monotonicity and partial compensation for integral non-linearity. Two stages are separated by a unity-gain operational amplifier, wherein the first stage is a 1-bit resistor string-converter, having one end at reference high voltage, and the other end at reference low voltage, and the second stage is a multi-bit resistor string converter. The architecture relieves matching accuracy necessary for 1-bit front end. Resistor mismatch is compensated by varying buffer amplifier offset-voltage, and ensuring amplifier output is halfway between reference voltages; this improves integral non-linearity, or absolute accuracy, by the amount of mismatch present in the resistor string. Buffer amplifier at output of second stage of DAC controls INL error by varying offset voltage.

Abstract: A sigma-delta modulator. The sigma-delta modulator comprises an integrator, a first quantizer, a dither generator and an adding device. An input terminal of the first quantizer and an input terminal of the dither generator are coupled to an output terminal of the integrator. The first quantizer generates a first random signal. The dither generator comprises a second quantizer for generating a second random signal, an input terminal thereof coupling to the output of the integrator; a random sequencer for receiving the first random signal and the second random signal to produce a third random signal output; and an attenuator for attenuating the third random signal to produce a dither signal to output. The dither signal is added to an input terminal of the integrator by the adding device.

Abstract: A longitudinally-coupled resonator mode SAW filter portion having at least two interdigital transducers (IDTs) is disposed on a piezoelectric substrate. At least one SAW resonator is electrically connected in parallel with the SAW filter portion such that the at least one SAW resonator is disposed between an input terminal or an output terminal and the SAW filter portion. The resonance point of the SAW resonator is disposed in the pass band of the SAW filter portion.

Abstract: A sigma delta modulator having an integrator with a first input for coupling to an analog signal and a second input for coupling to a reference voltage. A comparator is provided having a first input coupled to an output of the integrator and a second input for coupling to the reference voltage. The comparator produces signal having a logic state in accordance with the relative magnitude of signals at the first and second inputs thereof. The logic state is latched at the output of such comparator during latching transitions in a series of latching pulses fed to the comparator. A one-bit quantizer is provided for storing the logic state of at the output of the comparator at sampling transitions of a series of clock pulses fed to the one-bit quantizer. The series of clock pulses and the series of latching pulses are synchronized one with the other. Each one of the latching transitions occurs prior to a corresponding one of the sampling transitions.

Abstract: A 6-bit output code word is generated in response to every 4-bit input code word by referring to a set of encoding tables. The encoding tables contain output code words assigned to input code words, and contain encoding-table designation information accompanying each output code word. The encoding-table designation information designates an encoding table among the encoding tables which is used next to generate an output code word immediately following the output code word accompanied with the encoding-table designation information. Two redundant bits are added to every prescribed number of the successive generated output code words for digital-sum-variation control. The generated output code words and the added redundant bits are sequentially connected into a redundant-bit-added output-code-word sequence which follows predetermined run length limiting rules (1, k)RLL, where “k” denotes a predetermined natural number equal to 9.

Abstract: Encoding tables are accorded with variable-length encoding rules using a variable constraint length. A DSV control bit is periodically inserted into a first input bit stream to generate a second input bit stream. Every m-bit piece of the second input bit stream is encoded into an n-bit output signal forming at least a portion of an output code word by referring to the encoding tables. Thereby, the second input bit stream is converted into a first output bit stream composed of output code words and observing RLL (d, k). A sync word is inserted into the first output bit stream for every frame to generate a second output bit stream. A frame-end output code word is terminated at a position before a next-frame sync word. DSV control of the second output bit stream is implemented in response to the inserted DSV control bits.

Abstract: An encoder that includes a sensing device that senses encoding marks on a sensing surface that also includes one or more reference marks. The sensing device generates first and second encoder signals when the encoding marks pass the sensing device. The encoding signals define the direction of motion and degree of movement of the sensing surface. A register stores the position of the encoding surface relative to the sensing device. A controller receives the first and second encoder signals and increments or decrements the digital register based on the received first and second encoder signals. The encoder also includes a reference mark detector that generates a first reference mark signal when the first reference mark passes the reference mark detector. The controller resets the digital value to a first reference value when the encoder receives the first reference mark signal.