Abstract: An analog-to-digital converter includes an input buffer connected to an input terminal receiving an input signal through a first sampling switch, a comparator connected to the input buffer, a sampling capacitor connected between the input buffer and the comparator, and connected to a second sampling switch, a digital-to-analog converter connected to the comparator, and a controller, connected between the comparator and the digital-to-analog converter, configured to output a signal to the digital-to-analog converter based on the comparator.

Abstract: A continuous-time (CT) delta-sigma modulator (DSM) based analog to digital converter (ADC) in a radio receive chain supports a wide range of data rates in a power efficient way in a small die area. The ADC utilizes a 2nd order loop-filter with a single-amplifier loop-filter topology using a two stage Miller amplifier with a feed forward path and a push-pull output stage. High bandwidth operations utilize a “negative-R” compensation scheme at the amplifier input. Negative-R assistance is disabled for low data rate applications. With the negative-R assistance disabled, loop-filter resistor values are increased, instead of only the loop filter capacitor values to scale the noise transfer function (NTF), thereby limiting the capacitor area needed and enabling lower power operation. The NTF zero location is programmable allowing the NTF zero to be located near the intermediate frequency for different bandwidths to reduce the DSM quantization noise contribution for narrow-band (low data rate) applications.

Abstract: A non-linear converter comprising a non-linear voltage divider having a plurality of resistors representing a non-linear transfer function, an analog multiplexer having analog multiplexer inputs coupled to the non-linear voltage divider and configured to output an analog multiplexer output, the analog multiplexer chooses one of the plurality of resistors based on a logic signal and the non-linear transfer function, an analog comparator having an analog comparator first input configured to receive an analog input voltage, an analog comparator second input configured to receive the analog multiplexer output and the analog comparator configured to output a comparator voltage output and a logic loop coupled to the analog comparator and configured to receive the comparator voltage output and configured to output the logic signal, wherein the logic signal represents a linearized digital word.

Abstract: An analog-to-digital converter (“ADC”) includes an input terminal configured to receive an analog input signal. A first ADC circuit is coupled to the input terminal and includes a VCO. The first ADC circuit is configured to output a first digital signal in a frequency domain based on the analog input signal. The first digital signal includes an error component. A first DAC is configured to convert the first digital signal to an analog output signal. A first summation circuit is configured to receive the analog output signal, the analog input signal, and a loop filtered version of the analog input signal and extract the error component, and output a negative of the error component. A second ADC circuit is configured to convert the negative of the error component to a digital error signal. A second summation circuit is configured to receive the first digital signal and the digital error signal, and to output a digital output signal corresponding to the analog input at an output terminal.

Abstract: A digital unit cell, readout circuit for a digital unit cell and a method of operating an analog counter of a digital unit cell is disclosed. The readout circuit includes storage capacitor for storing a voltage remaining at an analog counter at the end of an integration period, and a comparator circuit. The comparator circuit compares a dummy voltage provided from the analog counter during a readout period to the voltage at the storage capacitor, and determines the voltage at the storage capacitor when the dummy voltage falls below the voltage at the storage capacitor.

Abstract: Embodiments of the present disclosure provide a comparator. The comparator includes a first current source circuit, a pre-amplifier circuit, an amplifier circuit, a comparison circuit, and an output circuit. The first current source circuit is configured to provide a first constant current to the pre-amplifier circuit. The pre-amplifier circuit is configured to amplify a first input signal into a first pre-amplified signal and amplify a second input signal into a second pre-amplified signal based on a first constant current. The amplifier circuit includes a current mirror and a load circuit. The load circuit comprises a differential diode-connected transistor. The comparison circuit is configured to compare the first amplified signal with the second amplified signal. The output circuit is configured to output a first voltage or a second voltage based on a result of the comparison.

Abstract: A real time digital trigger detection channel includes an event detector, a pulse former, a low pass filter, an analog-to-digital converter (ADC) and a Discrete Fourier Transform (DFT) processor coupled in series. The event detector is responsive to an applied input signal and the presence of information requiring digital trigger generation. The pulse former generates a pre-determined, limited length, stable pulse signal which is applied to an anti-aliasing, pulse shaping low pass filter. The resultant shaped pulse signal is converted to a sequence of sample values by the ADC, which in turn are applied to the DFT processor, which in turn calculates a discrete Fourier transform of the output sequence of ADC samples, performing trigger position calculation based on values determined by the DFT processor.

Abstract: An electronic device for decompressing compressed data includes a decoding subsystem having a symbol decoder and a second symbol resolver with a number of local symbol decoders and a symbol selector. The symbol decoder decodes a first symbol from a first code for which a symbol is available in a block of the compressed data and communicates a length of the code to the second symbol resolver. Each local symbol decoder, substantially in parallel with the decoding of the first symbol in the symbol decoder, decodes a respective symbol from a first code for which a symbol is available in a respective sub-block of the block of the compressed data. The second symbol resolver selects, as a second symbol, based on the length received from the symbol decoder, one of the respective symbols from the local symbol decoders. The decoding subsystem then provides the first and second symbols.

Abstract: Examples herein relate to decoding tokens using speculative decoding operations to decode tokens at an offset from a token decoded by a sequential decoding operation. At a checkpoint, a determination is made as to whether tokens to be decoded by the sequential and speculative decoding operations align. If there is alignment, the speculatively decoded tokens after a discard window are committed and made available for access. If there is not alignment, the speculatively decoded tokens are discarded. A miss in alignment and a fullness level of a buffer that stores speculatively decoded tokens are assessed to determine a next offset level for a start of speculative decoding. A size of a discard window can be set using a relationship based on the offset level to improve buffer utilization and to attempt to improve changes of alignments.

Abstract: A signal processing system includes an analog-to-digital converter (ADC) that is used to convert a first analog value into a first digital value and convert a second analog value into a second digital value. The ADC includes a first digital-to-analog converter (DAC) circuit and a second DAC circuit operating in different voltage domains. A first bit segment and a second bit segment of each digital value are determined via the first DAC circuit and the second DAC circuit, respectively. An analog injection value is injected to the second analog value, the analog injection value is converted from a digital injection value formed by a subset of bits of the second bit segment of the first digital value, and the second bit segment of the second digital value is derived from injecting the digital injection value to a digital value determined by the second DAC circuit.

Abstract: A switched-capacitor analog-to-digital converter (ADC) includes: a main digital-to-analog converter (DAC) circuit; a comparator coupled to the main DAC circuit and configured to determine whether the input to the comparator exceeds a pre-determined threshold; and a supplementary DAC circuit coupled to the main DAC circuit, wherein the switched-capacitor ADC is configured to operate in at least one of a first mode or a second mode, wherein in the first mode for measuring an offset of the switched-capacitor ADC, the supplementary DAC circuit is configured to shift a voltage at an output of the main DAC circuit by a first value having a first polarity, and wherein in the second mode for measuring a full-scale gain error of the switched-capacitor ADC, the supplementary DAC circuit is configured to shift the voltage at the output of the main DAC circuit by a second value having a second polarity opposite the first polarity.

Abstract: A multi-level capacitive digital-to-analog converter, comprises at least one capacitor switch circuit (100) including a differential operational amplifier (130) having a first input node (E130a) and a second input node (E130b). A first current path (101) is coupled to a first reference input terminal (E100a) to apply a first reference potential (RefP) and the second current path (102) is coupled to a second reference input terminal (E100b) to apply a second reference potential (RefN). The at least one capacitor switch circuit (100) comprises a first controllable switch (111) being arranged between the second input node (E130a) of the differential operational amplifier (130) and the first current path (101). The at least one capacitor switch circuit (100) comprises a second controllable switch (112) being arranged between the first input node (E130a) of the differential operational amplifier (130) and the second current path (102).

Abstract: A circuit includes an analog-to-digital converter (ADC) and a hysteresis circuit. The ADC is configured to generate a series of digital codes. The hysteresis circuit is configured to: (a) determine that a first digital code of the series of digital codes represents a change in a same direction as previous digital codes and store the first digital code in the register; and (b) determine that a second digital code of the series of digital codes represents a change in direction from previous digital codes, determine that the second digital code is less than a hysteresis value different than a preceding digital code, and not store the second digital code in the register.

Abstract: Apparatus and methods for reconfigurable antenna systems are provided herein. In certain configurations, an antenna system includes an antenna element, a tuning conductor adjacent to and spaced apart from the antenna element, and a switch electrically connected between the tuning conductor and a reference voltage, such as ground. The tuning conductor is operable to load the antenna element, and the switch selectively connects the tuning conductor to the reference voltage to provide tuning to the antenna element.

Abstract: A method and a circuit for measuring an absolute voltage signal, such that the circuit comprises: an A/D convertor, and a controller adapted for: a) obtaining a first digital reference value for a first reference signal having a positive temperature coefficient; b) obtaining a second digital reference value for a second reference signal having a negative temperature coefficient; c) obtaining a raw digital signal value for the signal to be measured, while applying a same reference voltage for step a) to c); and d) calculating the absolute voltage value in the digital domain using a mathematical function of the first and second digital reference value, and the raw digital signal value.

Abstract: An electronic circuit includes a first converting circuit, an amplifying circuit, and a second converting circuit. The first converting circuit outputs a first residual voltage associated with converting an analog signal into a first digital signal and a second residual voltage generated based on the first residual voltage. The amplifying circuit generates a third residual voltage by amplifying the first residual voltage through an amplifying path during a first time duration and generates a fourth residual voltage by amplifying the second residual voltage through the amplifying path during a second time duration after the first time duration. The second converting circuit generates a second digital signal associated with the analog signal by performing an interpolation operation based on the third residual voltage and the fourth residual voltage.

Abstract: An apparatus for calibrating a time-interleaved analog-to-digital converter including a plurality of time-interleaved analog-to-digital converter circuits is provided. The apparatus includes a clock generation circuit configured to generate a plurality of phase shifted clock signals for the plurality of time-interleaved analog-to-digital converter circuits and a reference clock signal. Further, the apparatus includes a reference signal generation circuit configured to generate a reference signal based on the reference clock signal. The reference signal is a square wave signal. The apparatus additionally includes a coupling circuit configured to controllably couple an input node of the time-interleaved analog-to-digital converter to either the reference signal generation circuit or to a signal node capable of providing an analog signal for digitization.

Abstract: The present invention includes: a first decoder that outputs mutually different two voltages as first and second selection voltages based on a first bit group of a digital data signal in a first selection state, and outputs one or both of the two voltages as the first and the second selection voltages in a second selection state; a second decoder that outputs mutually different two voltages as third and fourth selection voltages based on a second bit group of the digital data signal in the first selection state and outputs one voltage based on the second bit group as the third and the fourth selection voltages in the second selection state; and an amplifier circuit that averages a combination of the first and the second selection voltages or the third and the fourth selection voltages with predetermined weighting ratios and outputs the averaged voltage.

Abstract: An inductor bridge is provided with a flexible flat plate-shaped element body, a first connector, and a second connector. The element body includes therein an inductor portion. The inductor portion is configured by a spiral conductor pattern. The first connector is provided on the element body and is connected to a first circuit. The second connector is provided on the element body and is connected to a second circuit.

Abstract: A method for encoding and compressing a bit stream is provided. The method includes: receiving a bit stream; determining whether a first number of bits that are consecutive and identical in the bit stream is greater than or equal to a first preset value; and when the first number is greater than or equal to the first preset value, the first number of bits are encoded as a first code in a first encoding way, wherein the first code is composed of a first prefix and a first suffix, and the first prefix represents what the consecutive bits are and the first suffix represents the first number.