Abstract: A first photoresist layer is patterned with a first pattern that includes an opening in a region between areas of two adjacent via holes to be formed. The opening in the first photoresist is transferred into a template layer to form a line trench therein. The lateral dimension of the trench is reduced by depositing a contiguous spacer layer that does not fill the trench completely. An etch-resistant material layer is conformally deposited and fills the trench, and is subsequently recessed to form an etch-resistant material portion filling the trench. A second photoresist layer is applied and patterned with a second pattern, which includes an opening that includes areas of two via holes and an area therebetween. A composite pattern of an intersection of the second pattern and the complement of the pattern of the etch-resistant material portion is transferred through the template layer.

Abstract: A sensor package comprises a sensor chip bonded to an intermediate carrier, with the sensor element over an opening in the carrier. The package is for soldering to a board, during which the intermediate carrier protects the sensor part of the sensor chip.

Abstract: An object of the invention is to manufacture a semiconductor module small. A metal wire (212) connecting a control electrode (101) and a control terminal (21) rises to form a first angle (?1) from the control electrode (101) toward a first conductive portion (202), gradually goes in substantially parallel to the first conductive portion (202) as the metal wire approaches the first conductive portion (202), and is connected to the control terminal (21) to form a second angle (?2) smaller than the first angle (?1).

Abstract: To prevent light leakage and compensate for a step between a display region and a non-display region, a thin film transistor array substrate can include a base substrate having a display region and a non-display region, a plurality of pixel regions defined by gate lines and data lines crossing each other in the display region of the base substrate, a common line corresponding to between adjacent pixel regions, a thin film transistor and a color filter in each pixel region, a first dummy color filter between the adjacent pixel regions, a second dummy color filter in the non-display region on the base substrate, the second dummy color filter being provided at an upper surface thereof with at least one recess, and a protective film over the entire surface of the base substrate to cover the first and second dummy color filters and fill the recess.

Abstract: A method of forming a NAND flash memory includes forming a conductive area in a substrate, the conductive area extending along a direction that is perpendicular to the direction along which NAND strings extend, the conductive area connecting terminals of NAND strings. Discrete contact areas in the conductive area are contacted by discrete contact plugs, each contact plug contacting a corresponding contact area in the conductive area.

Abstract: A microelectromechanical systems (MEMS) structure having a stopper integrated with a MEMS substrate is provided. A first substrate has a dielectric layer arranged over the first substrate. The dielectric layer includes a device opening. A second substrate is arranged over and bonded to the first substrate through the dielectric layer. The second substrate includes a deflectable element arranged over the device opening. A stopper is integrated with the second substrate and protrudes from the deflectable element over the device opening. A method for manufacturing the MEMS structure is also provided.

Abstract: This invention provides a manufacturing method of a magnetoresistive effect element having a higher MR ratio than a conventional element. A manufacturing method of a magnetoresistive effect element of an embodiment of the invention includes: a step of forming a tunnel barrier layer on a substrate, on a surface of which one of a magnetization free layer and a magnetization fixed layer is formed; a step of cooling the substrate after the step of forming a tunnel barrier layer; a step of forming an other one of the magnetization free layer and the magnetization fixed layer on the tunnel barrier layer after the step of cooling; and a step of raising a temperature of the substrate after the step of forming the other one of the magnetization free layer and the magnetization fixed layer.

Abstract: A power semiconductor module includes a cooler; a plurality of power semiconductor units fixed on the cooler; and a bus bar unit connected electrically to the plurality of power semiconductor units. Each of the plurality of power semiconductor units includes a multilayered substrate including a circuit plate, an insulating plate, and a metal plate laminated in respective order; a semiconductor element fixed to the circuit plate; a wiring member having a printed circuit board and a plurality of conductive posts; external terminals connected electrically and mechanically to the circuit plate; and an insulating sealing material. The bus bar unit includes a plurality of bus bars mutually connecting the external terminals of the plurality of power semiconductor units.

Abstract: A reverse blocking IGBT is manufactured using a silicon wafer sliced from a single crystal silicon ingot which is manufactured by a floating method using a single crystal silicon ingot manufactured by a Czochralski method as a raw material. A separation layer for ensuring a reverse blocking performance of the reverse blocking IGBT is formed by diffusing impurities implanted into the silicon wafer using a thermal diffusion process. The thermal diffusion process for forming the separation layer is performed in an inert gas atmosphere at a temperature equal to or more than 1290° C. and less than the melting point of silicon. In this way, no crystal defect occurs in the silicon wafer and it is possible to prevent the occurrence of a reverse breakdown voltage defect or a forward defect in the reverse blocking IGBT and thus improve the yield of a semiconductor element.

Abstract: A laminated semiconductor device includes: a first semiconductor element provided with a photoelectric conversion region on its main surface; an extended portion extended outwardly from a side end surface of the first semiconductor element; a redistribution layer formed on a first surface of the extended portion; a second semiconductor element provided on the main surface of the first semiconductor element so as to extend to the extended portion from an outside of the photoelectric conversion region, the second semiconductor element being electrically connected to the first semiconductor element and the redistribution layer; and a first electrode pad formed on the redistribution layer and electrically connected to the second semiconductor element via the redistribution layer.

Abstract: A method of manufacturing a silicon carbide semiconductor device includes forming on a front surface of a silicon carbide substrate of a first conductivity type, a silicon carbide layer of the first conductivity type of a lower concentration; selectively forming a region of a second conductivity type in a surface portion of the silicon carbide layer; selectively forming a source region of the first conductivity type in the region; forming a source electrode electrically connected to the source region; forming a gate insulating film on a surface of the region between the silicon carbide layer and the source region; forming a gate electrode on the gate insulating film; forming a drain electrode on a rear surface of the substrate; forming metal wiring comprising aluminum for the device, the metal wiring being connected to the source electrode; and performing low temperature nitrogen annealing after the metal wiring is formed.

Abstract: The present disclosure discloses a MOSFET and a method for manufacturing the same, wherein the MOSFET comprises: an SOI wafer comprising a semiconductor substrate, a buried insulating layer on the semiconductor substrate, and a semiconductor layer on the buried insulating layer; a gate stack on the semiconductor layer; a source region and a drain region in the semiconductor layer on both sides of the gate stack; and a channel region in the semiconductor layer and located between the source region and the drain region, wherein the MOSFET further comprises a back gate which is located in the semiconductor substrate and has a first doped region as a lower portion of the back gate and a second doped region as an upper portion of the back gate, and the second doped region of the back gate is self-aligned with the gate stack. The MOSFET can adjust a threshold voltage by changing doping type and doping concentration of the back gate.

Abstract: A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.

Abstract: A semiconductor device includes on an n-type semiconductor substrate of silicon carbide, an n-type semiconductor layer, a p-type base region, an n-type source region, a p-type contact region, a gate insulating film, a gate electrode, and a source electrode. The semiconductor device has a drain electrode on a back surface of the semiconductor substrate. On a surface of the gate electrode, an interlayer insulating film is disposed. The interlayer insulating film has plural layers among which, one layer is formed by a silicon nitride film. With such a structure, degradation of semiconductor device properties are suppressed. Further, increases in the number of processes at the time of manufacturing are suppressed.

Abstract: A power semiconductor device is disclosed having a power semiconductor element with an upper and lower side, the upper side being located opposite to the lower side; a first and second electrode, and a housing, wherein the power semiconductor element is arranged between the first and second electrode such, that the upper side comprises a first contact portion being in contact with the first electrode and a first free portion not being in contact with the first electrode, and wherein the lower side at least comprises a second contact portion being in contact with the second electrode, and wherein a channel is provided fluidly connecting at least a part of the first free portion with a predetermined degassing point of the housing for guiding an overpressure, which overpressure results from plasma and/or gas occurring in a failure mode, from the first free portion to the predetermined degassing point.

Abstract: An apparatus can include a first electrode on a planarization layer, an organic emission layer on the first electrode, a first bank and a second bank on the planarization layer and configured to surround the organic emission layer, and an anti-moisture unit on a portion of the planarization layer and a portion of the second bank, wherein the anti-moisture unit is configured to suppress moisture permeation through the second bank and the planarization layer.

Abstract: Embodiments of the present invention provide a process that maintains a “keep cap” metal nitride layer on PFET devices within a CMOS structure. The keep cap metal nitride layer is in place while an N-type work function metal is formed on the NFET devices within the CMOS structure. A sacrificial rare earth oxide layer, such as a lanthanum oxide layer is used to facilitate removal of the n-type work function metal selective to the keep cap metal nitride layer.

Abstract: A vertical JFET made by a process using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A maskless self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. Optionally the channel may be doped via angled implantation, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.

Abstract: A vertical JFET with a ladder termination may be made by a method using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A mask-less self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. Optionally the channel may be doped via angled implantation, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.

Abstract: A nitride semiconductor device according to the present disclosure includes a substrate; a first nitride semiconductor layer which is formed on the substrate, and which has a C-plane as a main surface; a second nitride semiconductor layer which is formed on the first nitride semiconductor layer, and which has p-type conductivity; and a first opening which is formed in the second nitride semiconductor layer, and which reaches the first nitride semiconductor layer. The nitride semiconductor device further includes a third nitride semiconductor layer which is formed so as to cover the first opening in the second nitride semiconductor layer; a first electrode which is formed on the third nitride semiconductor layer so as to include a region of the first opening; and a second electrode which is formed on the rear surface of the substrate.