Abstract: A plasma processing method for forming a film on a substrate using a gas processed by a plasma. The plasma processing method for forming a film includes the steps of forming a CF film on the substrate by using a CaFb gas (here, a is a counting number, and b is a counting number which satisfies an equation of “b=2×a?2”), processing the CF film with the gas processed by the plasma, and forming an insulating film on the CF film processed by using an insulating material processed with the plasma.

Abstract: A strained channel transistor structure and methods of forming a semiconductor device are presented. The transistor structure includes a strained channel region having a first semiconductor material with a first natural lattice constant. A gate dielectric layer overlying the strained channel region, a gate electrode overlying the gate dielectric layer and a source region and drain region oppositely adjacent to the strained channel region are provided. One or both of the source region and drain region include a stressor region having a second semiconductor material with a second natural lattice constant different from the first natural lattice constant. The stressor region has graded concentration of a dopant impurity and/or of a stress inducing molecule.

Abstract: Integrated circuits (IC) and a method of fabricating an IC, where the structure of the IC incorporates a back-end-of-the-line (BEOL) thin film resistor below a first metal layer to achieve lower topography are disclosed. The resistor directly contacts any one of: a contact metal in the front-end-of-the-line (FEOL) structure; first metal layer in the BEOL interconnect; or the combination thereof, to avoid the necessity of forming contacts with differing heights or contacts over varying topography.

Abstract: Example embodiments relate to a biosensor using a nanoscale material as a channel of a transistor and a method of fabricating the same. A biosensor according to example embodiments may include a plurality of insulating films. A first signal line and a second signal line may be interposed between the plurality of insulating films. A semiconductor nanostructure may be disposed on the plurality of insulating films, the semiconductor nanostructure having a first side electrically connected to the first signal line and a second side electrically connected to the second signal line. A plurality of probes may be coupled to the semiconductor nanostructure. A biosensor according to example embodiments may have a reduced analysis time.

Abstract: A recess gate of a semiconductor device is provided, comprising: a substrate having a recess formed therein; a metal layer formed at the bottom of the recess; a polysilicon layer formed over the metal layer; and a source region and a drain region formed adjacent to the polysilicon layer and spaced from the metal layer.

Abstract: A full-color organic light emitting diode display device and a method of fabricating the same. The display device includes a substrate having red, green and blue light emitting regions, a first electrode on the substrate, an organic layer on the first electrode and including red, green and blue light emitting layers respectively corresponding to the red, green and blue light emitting regions, and a second electrode on the entire surface of the substrate. Here, the organic layer includes a hole injection layer and an electron transport layer, and the organic layer in the red light emitting region includes a hole suppression layer including a material in the electron transport layer. The method includes forming the hole suppression layer on the red light emitting layer in the red light emitting region. In the method, the hole suppression layer is formed of a material for forming the electron transport layer.

Abstract: Systems and methods are disclosed for bonding of semiconductor, metal, metal-ceramic or combinations of these substrates using microwave energy. In some embodiments, metal-ceramic substrates carrying semiconductor substrates can be bonded simultaneously through a thin interlayer metal to a metal substrate by using microwave energy. In some embodiments, other substrate combinations can be bonded by using microwave energy. High intensity microwave energy is applied to the substrate assembly positioned within a microwave cavity. A process of selective heating can occur in the thin interlayer metal enhanced by the presence of third microwave absorbing substrate, resulting in melting of the thin interlayer metal to facilitate bonding of the two substrates. Some of the advantages associated with such bonding process are disclosed.

Abstract: A dielectrically isolated semiconductor device of high reliability is provided by realizing a fine and deep element isolating region which can prevent dislocation of an oxide film as an insulation layer by oxidation-induced stress. The dielectrically isolated semiconductor device includes an SOI substrate supporting an active element layer deeper than an expanded distance of a depletion layer subjected to the highest voltage applied to the device, and an element isolating region which encloses the active element layer. The element isolating region contains a deep trench which comes into contact with the insulation layer, and which is filled with n heavily doped layers on both side walls, second insulation films each adjacent to the n heavily doped layer and a polycrystalline semiconductor layer formed between the second insulation films.

Abstract: A fabricating process of a chip package structure is provided. First, a first substrate having a plurality of first bonding pads and a second substrate having a plurality of second bonding pads are provided, wherein bumps are formed on the first bonding pads of the first substrate. A first two-stage adhesive layer is formed on the first substrate and is B-stagized to form a first B-staged adhesive layer. A second two-stage adhesive layer is formed on the second substrate and is B-stagized to form a second B-staged adhesive layer. Then, the first substrate and the second substrate are bonded via the first and second B-staged adhesive layer such that the bumps pierce through the second B-staged adhesive layer and are electrically connected to the second bonding pads, wherein each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps.

Abstract: A CMOS image sensor and fabricating method thereof are disclosed. The method includes forming a plurality of photodiode regions on a semiconductor substrate, forming a plurality of color filters respectively corresponding to the photodiode regions, forming a planarization layer on the color filters, forming a protective layer on the planarization layer, and forming a microlens layer comprising a plurality of microlenses corresponding to the photodiode regions by depositing a low-temperature oxide layer on the protective layer and then patterning the low-temperature oxide layer. After the planarization layer is formed, the protective layer is formed by plasma processing. Thus, the planarization layer can be protected from chemical penetration via numerous pin holes in the microlens layer in the course of wet processing. Accordingly, the method prevents the microlens from lifting from the planarization layer.

Abstract: In a wafer, a plurality of basic chips F is arranged therein. The basic chip F has a memory capacity of i-mega bytes. By dicing, a memory chip including four basic chips F is cut out of the wafer. The memory chip has a memory capacity of 4×i-mega bytes. A dicing line is interposed between four basic chips F configuring the memory chip, Four basic chips F can change word organization by a control signal individually.

Abstract: A method for manufacturing a liquid crystal display includes simultaneously forming a gate electrode and a gate bus line on a transparent dielectric substrate, simultaneously forming a channel layer, an ohmic contact layer, and source/drain electrodes by forming a gate insulation film, an amorphous silicon film, a doped amorphous silicon film, and a metal film on the transparent dielectric substrate on which the gate electrode and the gate bus line are formed and etching the metal film, the amorphous silicon film, and the doped amorphous silicon film, and forming a pixel electrode by forming a protective film and a transparent metal film on the transparent dielectric substrate upon which the source/drain electrodes are formed and finely etching the transparent metal film through a lift-off process using a stripper solution.

Abstract: Growing a first nitride semiconductor layer on an AlxGayIn1-x-yN(0?x?1, 0<y?1, 0<x+y?1)layer, reducing the thickness of the first nitride semiconductor layer by growth interruption and, growing a second nitride semiconductor layer having a band gap energy higher than that of the first nitride semiconductor layer on the first nitride semiconductor layer with the reduced thickness and a light emitting device using the growth method.

Abstract: A wafer level packaging method is revealed. Firstly, a wafer with a plurality of bumps disposed on a surface is provided. Placing a dielectric tape on a mold plate is followed. Then, the wafer is laminated with the mold plate to make the dielectric tape be compliantly bonded to the surface of the wafer and to make the bumps be embedded in the dielectric tape. After removing the mold plate, flattening the dielectric tape to form a plurality of exposed surfaces of the bumps wherein the exposed surfaces and the flattened surface of the dielectric tape are coplanar. Therefore, the exposed surfaces of the bumps can be regarded as effective alignment points for easy pattern recognition of the wafer level packaged wafers during singulation process.

Abstract: The present invention provides a process of producing a porous insulating film effective as an insulating film constituting a semiconductor device and a process of producing a porous insulating film having high adhesion to a semiconductor material, which is in contact with the upper and lower interfaces of the insulating film. Gas containing molecule vapor of at least one or more organic silica compounds, which have a cyclic silica skeleton in its molecule and have at least one or more unsaturated hydrocarbon groups bound with the cyclic silica skeleton is introduced into plasma to grow a porous insulating film on a semiconductor substrate.

Abstract: Systems and methods are disclosed for bonding of substrates using microwave energy. In some embodiments, semiconductor substrates can be bonded through a thin interlayer metal to a metal substrate by using microwave energy. High intensity microwave energy is applied to the substrate assembly positioned within a microwave cavity. A process of selective heating can occur in the thin interlayer metal, resulting in melting of the thin interlayer metal to facilitate bonding of the two substrates. Some of the advantages associated with such bonding process are disclosed.

Abstract: A memory cell device of the type that includes a memory material switchable between electrical property states by application of energy, situated between first and second (“bottom” and “top”) electrodes has a top electrode including a larger body portion and a stem portion. The memory material is disposed as a layer over a bottom electrode layer, and a base of the stem portion of the top electrode is in electrical contact with a small area of the surface of the memory material. Methods for making the memory cell are described.

Abstract: Methods of fabricating a dual control gate non-volatile memory array are described. Parallel strips of floating gate material are formed over the substrate in a first direction but separated from it by a tunnel dielectric. In the gaps between these strips control gate material is formed forming a second set of parallel strips but insulated from both the adjacent floating gate stripes and the substrate. Both sets of strips are isolated in a second direction perpendicular to the first direction forming an array of individual floating gates and control gates. The control gates formed from an individual control gate strip are then interconnected by a conductive wordline such the potential on individual floating gates are controlled by the voltages on two adjacent wordlines. In other variations either the floating gates or the control gates may be recessed into the original substrate.

Abstract: A method of forming a nitride film by hydride vapor phase epitaxy, the method including: sequentially disposing at least one group III metal source including impurities and a substrate in an external reaction chamber and an internal reaction chamber sequentially located in the direction of gas supply and heating each of the external reaction chamber and the internal reaction chamber at a growth temperature; forming a metal chloride by supplying hydrogen chloride gas and carrier gas into the external reaction chamber to react with the group III metal source and transferring the metal chloride to the substrate; and forming the nitride film doped with the impurities on the substrate by reacting the transferred metal chloride with nitrogen source gas supplied to the internal reaction chamber.

Abstract: The present invention is directed to a diode with an asymmetric silicon germanium anode and methods of making same. In one illustrative embodiment, the diode includes an anode comprising a P-doped silicon germanium material formed in a semiconducting substrate, an N-doped silicon cathode formed in the semiconducting substrate, a first conductive contact that is conductively coupled to the anode and a second conductive contact that is conductively coupled to the cathode.