Abstract: A spin-orbit torque device is disclosed, which includes: a magnetic layer; and a non-magnetic layer adjacent to the magnetic layer and comprising a spin-Hall material, wherein the spin-Hall material comprises NixCu1-x alloy, and x is in a range from 0.4 to 0.8.

Abstract: Semiconductor memory cells, array and methods of operating are disclosed. In one instance, a memory cell includes a bi-stable floating body transistor and an access device; wherein the bi-stable floating body transistor and the access device are electrically connected in series.

Abstract: Methods of reflowing electrically conductive elements on a wafer may involve directing a laser beam toward a region of a surface of a wafer supported on a film of a film frame to reflow at least one electrically conductive element on the surface of the wafer. In some embodiments, the wafer may be detached from a carrier substrate and be secured to the film frame before laser reflow. Apparatus for performing the methods, and methods of repairing previously reflowed conductive elements on a wafer are also disclosed.

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, forming an etch stop layer on the MTJ stack, forming a first spin orbit torque (SOT) layer on the etch stop layer, and then patterning the first SOT layer, the etch stop layer, and the MTJ stack to form a MTJ.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) stack on a substrate; forming a first spin orbit torque (SOT) layer on the MTJ stack; forming a first hard mask on the first SOT layer; and using a second hard mask to pattern the first hard mask, the first SOT layer, and the MTJ stack to form a MTJ.

Abstract: An organic light emitting display device includes a substrate, a light emitting structure, an undercut structure, and a functional module. The substrate includes an opening region, a peripheral region surrounding the opening region, and a display region surrounding the peripheral region. The substrate has a groove in the peripheral region and an opening in the opening region. The light emitting structure is in the display region on the substrate. The undercut structure is inside the groove in the substrate. The undercut structure includes a sacrificial metal pattern having a first width and at least one insulating layer pattern having a second width greater than the first width. The functional module is in the opening of the substrate.

Abstract: In an embodiment, a method includes: aligning a first package component with a second package component, the first package component having a first region and a second region, the first region including a first conductive connector, the second region including a second conductive connector; performing a first laser shot on a first portion of a top surface of the first package component, the first laser shot reflowing the first conductive connector of the first region, the first portion of the top surface of the first package component completely overlapping the first region; and after performing the first laser shot, performing a second laser shot on a second portion of the top surface of the first package component, the second laser shot reflowing the second conductive connector of the second region, the second portion of the top surface of the first package component completely overlapping the second region.

Abstract: A first mask and a second mask are sequentially provided to perform a multi-step exposure and development processes. Through proper overlay design of the first mask and the second mask, conductive wirings having acceptable overlay offset are formed.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a polymer base layer, a backside redistribution layer (RDL) over the polymer base layer; a molding layer over the backside RDL; a polymer layer over the molding layer; a front side RDL over the polymer layer; and a metal-insulator-metal (MIM) capacitor vertically passing through the molding layer, the MIM capacitor including a first electrode, an insulation layer and a second electrode, wherein the insulation layer surrounds the first electrode, and the second electrode surrounds the insulation layer, and the molding layer surrounds the second electrode. An associated method for manufacturing a semiconductor structure is also disclosed.

Abstract: An integrated semiconductor device having a metallic element formed between a capacitor with and a doped region.

Abstract: A display apparatus includes a substrate including a penetrating area including a substrate hole, and a separating area surrounding the penetrating area, a first buffer layer including a first-buffer lower layer on the substrate, and a first-buffer upper layer on the first-buffer lower layer, a first TFT including a first semiconductor pattern on the first-buffer upper layer, and a first gate electrode overlapping with the first semiconductor pattern under conditions that a first gate insulating film is interposed therebetween, and first source/drain electrodes connected to the first semiconductor pattern, a second TFT, a separation structure disposed in the separating area of the substrate while including a first separation layer having the same stacked structure as the first-buffer upper layer, a second separation layer having the same stacked structure as the first gate insulating film, and a third separation layer having the same stacked structure as the first gate electrode.

Abstract: An integrated circuit includes a doped region having a first conductivity type formed in a semiconductor substrate having a second conductivity type. A dielectric layer is located between the doped region and a surface plane of the semiconductor substrate, and a polysilicon layer is located over the dielectric layer. First, second, third and fourth terminals are connected to the doped region, the first and third terminals defining a conductive path through the doped region and the second and fourth terminals defining a second conductive path through the doped region, the second path intersecting the first path.

Abstract: Techniques are provided to fabricate semiconductor devices having a nanosheet field-effect transistor device disposed on a semiconductor substrate. The nanosheet field-effect transistor device includes a nanosheet stack structure including a semiconductor channel layer and a source/drain region in contact with an end portion of the semiconductor channel layer of the nanosheet stack structure. A trench formed in the source/drain region is filled with a metal-based material. The metal-based material filling the trench in the source/drain region mitigates the effect of source/drain material overfill on the contact resistance of the semiconductor device.

Abstract: Disclosed herein is a sub-pixel circuit for a display device. The sub-pixel circuit has a driving TFT and at least one switching TFT. The at least one switching TFT is an oxide TFT. The sub-pixel circuit additionally has at least one storage capacitor wherein the storage capacitor has a capacitance between about 1 fF and about 55 fF.

Abstract: An organic light emitting diode (OLED) display may include: an OLED configured to emit light of wavelength ?; an encapsulation layer encapsulating the OLED, the encapsulation layer including: a first inorganic layer disposed on the OLED, the first inorganic layer including: one or more first layers having a first refractive index (n1) and a first thickness substantially equal to ?/(4*n1); and one or more second layers having a second refractive index (n2) and a second thickness substantially equal to ?/(4*n2), wherein the second refractive index is smaller than the first refractive index, and wherein the one or more first layers and the one or more second layers are alternatingly stacked on one another.

Abstract: A display panel is disclosed. The disclosed display panel includes a thin film transistor substrate, a plurality of micro LEDs arranged on one surface of the thin film transistor substrate, a plurality of first connection pads disposed on the one surface of the thin film transistor substrate, a plurality of second connection pads disposed on the other surface of the thin film transistor substrate that faces the one surface, and a plurality of connection wirings disposed on a side surface of the thin film transistor substrate for electrically connecting each of the plurality of first connection pads and the plurality of second connection pads, wherein at least one of an edge region on the one surface and an edge region on the other surface of the thin film transistor substrate includes a cutting area which is cut in an inward direction of the thin film transistor substrate.

Abstract: A light-emitting diode (LED) device includes a first epitaxial layered structure having an upper surface having different first and second regions, a second epitaxial layered structure spaced-apart disposed on the first epitaxial layered structure, a light conversion layer formed on the first region, a bonding unit disposed on the light conversion layer, the bonding unit and the light conversion layer interconnecting the first and second epitaxial layered structures, and an electrically conductive structure formed on the second region and electrically connects the first and second epitaxial layered structures. A method for manufacturing the LED device is also disclosed.

Abstract: A display panel and a display device. The display panel includes a display panel main body and a cover plate; the display panel main body has a light emitting surface, and the cover plate covers the light emitting surface of the display panel main body; the light emitting surface includes a flat light emitting region and a curved light emitting region, the cover plate includes a curved portion covering the curved light emitting region; in a direction from the flat light emitting region to the curved light emitting region, thicknesses of positions of the curved portion gradually decrease.

Abstract: Various embodiments of the present application are directed towards an integrated circuit comprising a resistive random-access memory (RRAM) cell with recessed bottom electrode sidewalls to mitigate the effect of sidewall plasma damage. In some embodiments, the RRAM cell includes a lower electrode, a data storage element, and an upper electrode. The lower electrode includes a pair of recessed bottom electrode sidewalls respectively on opposite sides of the lower electrode. The data storage element overlies the lower electrode and includes a pair of storage sidewalls. The storage sidewalls are respectively on the opposite sides of the lower electrode, and the recessed bottom electrode sidewalls are laterally spaced from and laterally between the storage sidewalls. The upper electrode overlies the data storage element.

Abstract: A sensor device comprising: a lead frame; a first/second semiconductor die having a first/second sensor structure at a first/second sensor location, and a plurality of first/second bond pads electrically connected to the lead frame; the semiconductor dies having a square or rectangular shape with a geometric center; the sensor locations are offset from the geometrical centers; the second die is stacked on top of the first die, and is rotated by a non-zero angle and optionally also offset or shifted with respect to the first die, such that a perpendicular projection of the first and second sensor location coincide.