Patents Examined by Latanya N Crawford
  • Patent number: 10446436
    Abstract: A method of protecting a dielectric during fabrication is provided. A conductive layer is patterned to form a first conductive shape on a first portion of a dielectric layer and a second conductive shape on a second portion of the dielectric layer. A conductive trace is formed over at least a portion of the second conductive shape. The conductive trace electrically connects the first conductive shape with a substrate tie. An interconnect layer is coupled to the first conductive shape. The conductive trace is etched to electrically isolate the first conductive shape from the substrate tie.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: October 15, 2019
    Assignee: NXP USA, INC.
    Inventors: William Ernest Edwards, Brian George Anthony
  • Patent number: 10446510
    Abstract: A process of forming a semiconductor apparatus is disclosed. The process includes steps of: depositing a first metal layer containing Ni in a back surface of a substrate, plating the back surface of the substrate so as to expose the first metal layer in a portion of the scribe line, depositing a third metal layer on the whole back surface of the substrate, and selectively removing the third metal layer in the portion of the scribe line so as to leave the first metal layer in the scribe line.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: October 15, 2019
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventor: Masaomi Emori
  • Patent number: 10439061
    Abstract: A front surface electrode common to a plurality of unit cells is provided substantially all over an active region of a semiconductor element. A plurality of electrode pads on the front surface electrode are closer to the outer peripheral portion side than the central portion of the active region. Different wires are joined to substantially the center of each electrode pad. The active region is divided into two or more segments so that the segments are aligned along the path of current flowing through the front surface electrode, and unit cells different in conduction ability are disposed respectively in each segment. Unit cells lowest in conduction ability are in the first segment farthest from junctions of the wires and electrode pads, and the unit cells are disposed so that the farther apart from the junctions of the wires and electrode pads, the lower in conduction ability the unit cells are.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: October 8, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Takeyoshi Nishimura
  • Patent number: 10438944
    Abstract: When an ESD element is operated, for the purpose of suppressing heat generation and causing uniform current to flow through all channels of all transistors included in the ESD element, various substrate potentials existing in the transistors and the channels of a multi finger type ESD element are electrically connected via a low resistance substrate, and further, are set to a potential that is different from a Vss potential. In this manner, the current is uniformized and heat generation is suppressed through low voltage operation to improve an ESD tolerance.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: October 8, 2019
    Assignee: ABLIC Inc.
    Inventor: Tomomitsu Risaki
  • Patent number: 10424566
    Abstract: An electronic device comprises a carrier, an emitter, a detector, a separation wall and a light shielding layer. The emitter is disposed on a first portion of the top surface of the carrier. The detector is disposed on a second portion of the top surface of the carrier. The separation wall is disposed on the top surface of the carrier between the emitter and the detector. The light shielding layer disposed adjacent to the top surface of the carrier and extends from the separation wall to the second portion of the carrier.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: September 24, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chung-Wei Hsu, Hsin-Ying Ho, Hsun-Wei Chan
  • Patent number: 10411085
    Abstract: A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: September 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chiun Lin, Po-Nien Chen, Chen Hua Tsai, Chih-Yung Lin
  • Patent number: 10399306
    Abstract: Provided is a sheet 2 for forming a protective film including a protective film-forming film 1 of which the light transmittance at a wavelength of 1600 nm is 25% or greater, and light transmittance at a wavelength of 550 nm is 20% or less, and a release sheet 21 which is laminated on one or both surfaces of the protective film-forming film 1. According to such a sheet 2 for forming a protective film, cracks existing in a workpiece or a manufactured product obtained by processing the workpiece can be inspected and a protective film in which grinding marks existing in the workpiece or the manufactured product are not visually recognized can be formed.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: September 3, 2019
    Assignee: Lintec Corporation
    Inventors: Naoya Saiki, Daisuke Yamamoto, Hiroyuki Yoneyama, Ken Takano
  • Patent number: 10381509
    Abstract: The present embodiments relate a light emitting device.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: August 13, 2019
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Jung Yeop Hong, Myung Hee Kim
  • Patent number: 10373906
    Abstract: Structures and formation methods of a semiconductor device structure are provided. A method includes depositing a first layer including Al atoms to cover a first dielectric layer in a first conductive feature. The method also includes depositing a second layer including N atoms over the first layer. The first layer and the second layer form an etch stop layer including aluminum nitride. The etch stop layer includes vacancies and has an atomic percentage of Al to Al and N. The method also includes filling the vacancies in the etch stop layer with additional N atoms to reduce the atomic percentage of Al to Al and N. In addition, the method includes forming a second dielectric layer over the etch stop layer. The method also includes forming a second conductive feature in the second dielectric layer and the etch stop layer to be connected to the first conductive feature.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: August 6, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jyh-Nan Lin, Tsung-Dar Lee, Li Chen
  • Patent number: 10366945
    Abstract: A lead frame includes at least one row of a plurality of unit regions arranged in a first direction. Each of the unit regions includes: a first lead; a second lead; and an isolation region configured to isolate the first lead from the second lead, the isolation region including a bent portion that is located at an end part of the second lead. The first lead has an extending portion extending along the end part of the second lead. The plurality of unit regions includes a first unit region, and a second unit region that is adjacent to the first unit region in the first direction. The first lead of the first unit region is connected to the first lead or second lead of the second unit region via the extending portion.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: July 30, 2019
    Assignee: NICHIA CORPORATION
    Inventor: Takuya Nakabayashi
  • Patent number: 10361195
    Abstract: An embodiment includes a semiconductor device, comprising: a substrate; a continuous diffusion region disposed on the substrate; a first gate structure disposed on the continuous diffusion region; a second gate structure disposed on the continuous diffusion region; an isolation gate structure disposed between the first gate structure and the second gate structure and disposed adjacent to the both the first gate structure and the second gate structure; a first diffusion region of the continuous diffusion region disposed between the first gate structure and the isolation gate structure; a second diffusion region of the continuous diffusion region disposed between the second gate structure and the isolation gate structure; a conductive layer disposed on the first and second diffusion regions; and an isolation gate contact disposed over the isolation gate structure and electrically insulated from the first diffusion region.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: July 23, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Rwik Sengupta, Mark S. Rodder
  • Patent number: 10361160
    Abstract: This disclosure provides a package structure and its fabrication method. The package structure includes: a conductive pattern layer having a bump region and a wiring region, the bump region comprising a plurality of conductive bumps and a first dielectric material surrounding the plurality of conductive bumps, the wiring region comprising a plurality of first conductive wires and a second dielectric material covering and surrounding the plurality of first conductive wires; a circuit device with a plurality of connecting terminals disposed on the bump region, each of the connecting terminals corresponding with one of the conductive bumps; an insulation sealant formed on the second dielectric material and around sidewalls of the circuit device; and a third dielectric material covering the circuit device and the wiring region.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: July 23, 2019
    Assignee: PHOENIX & CORPORATION
    Inventor: Shih-Ping Hsu
  • Patent number: 10355071
    Abstract: A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: July 16, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chiun Lin, Po-Nien Chen, Chen Hua Tsai, Chih-Yung Lin
  • Patent number: 10340256
    Abstract: A display device is provided. The display device includes a substrate having a surface including a display area and a non-display area adjacent to the display area; a plurality of light-emitting diodes disposed on the display area of the substrate, wherein the light-emitting diode includes a contact electrode; and an anisotropic conductive layer disposed between the substrate and the plurality of light-emitting diodes, wherein the anisotropic conductive layer has a cross-sectional sidewall profile, and at least a part of the cross-sectional sidewall profile of the anisotropic conductive layer is in a shape of curve.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: July 2, 2019
    Assignee: INNOLUX CORPORATION
    Inventors: Yuan-Lin Wu, Kuan-Feng Lee, Wei-Cheng Chu
  • Patent number: 10326102
    Abstract: A flexible display apparatus includes a substrate, a thin film encapsulation layer, a plurality of spacers, and at least one layer of a blocking dam in the non-display region. The substrate includes a display region having a plurality of pixels and a non-display region adjacent to the display region. The thin film encapsulation layer is over the substrate. The spacers are between the substrate and the thin film encapsulation layer and are arranged around a pixel region. A different arrangement of spacers are in a center region and an edge region of the display region. The different arrangement may correspond to at least one of a size and a number of the spacers.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: June 18, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventor: Sungun Park
  • Patent number: 10325880
    Abstract: Representative implementations of devices and techniques provide a hybrid interposer for 3D or 2.5D package arrangements. A quantity of pockets is formed on a surface of a carrier in a predetermined pattern. The pockets are filled with a reflowable conductive material. Chip dice are coupled to the interposer carrier by fixing terminals of the dice into the pockets. The carrier may include topside and backside redistribution layers to provide fanout for the chip dice, for coupling the interposer to another carrier, board, etc. having a pitch greater than that of the chip dice.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: June 18, 2019
    Inventors: Charles G. Woychik, Cyprian Emeka Uzoh, Sangil Lee, Liang Wang, Guilian Gao
  • Patent number: 10325900
    Abstract: A layout includes a plurality of cells and at least one dummy gate electrode continuously extends across the cells. Since the dummy gate electrode is electrically conductive, the dummy gate electrode can be utilized for interconnecting the cells. That is, some signals may travel through the dummy gate electrode rather than through a metal one line or a metal two line. Therefore, an amount of metal one lines and/or metal two lines for interconnecting the cells can be reduced.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: June 18, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Chung-Te Lin, Ting-Wei Chiang, Hui-Zhong Zhuang, Pin-Dai Sue, Li-Chun Tien
  • Patent number: 10295875
    Abstract: A pixel structure in a pixel for used in a display panel has a plurality of grooves made on a substrate and a plurality of conducting lines formed in the grooves. The conducting line can be made from a silver or copper conductive ink to provide a low-resistance line served as a gate line, common line or source line. In a pixel having a storage capacitor and a TFT with a gate electrode, a source electrode and a drain electrode, the gate electrode is connected to a gate line and a source electrode and one of the capacitor electrodes in the storage capacitor is connected to a common line. At least part of one or more of the gate electrode and the source electrode is disposed on top of and in contact with the surface of one or more conducting lines.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: May 21, 2019
    Assignee: A.U. Vista, Inc.
    Inventors: Fang-Chen Luo, Willem den Boer, Seok-Lyul Lee
  • Patent number: 10297719
    Abstract: A micro-light emitting diode (micro-LED) device includes a receiving substrate and a micro-LED. The micro-LED includes a first type semiconductor layer, a second type semiconductor layer, a current controlling layer, at least one reflective layer, and at least one first electrode. The second type semiconductor layer is joined with the first type semiconductor layer. The current controlling layer is joined with one of the first type semiconductor layer and the second type semiconductor layer, the current controlling layer having at least one opening therein. The reflective layer electrically is coupled with the first type semiconductor layer. The first electrode is disposed on a surface of the reflective layer facing the receiving substrate. The first electrode forms an adhesive bonding system with the receiving substrate.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: May 21, 2019
    Assignee: MIKRO MESA TECHNOLOGY CO., LTD.
    Inventors: Li-Yi Chen, Shih-Chyn Lin, Hsin-Wei Lee, Pei-Yu Chang
  • Patent number: 10290747
    Abstract: MIS capacitors are formed using a finned semiconductor structure. A highly doped region including the fins is formed within the structure and forms one plate of a MIS capacitor. A metal layer forms a second capacitor plate that is separated from the first plate by a high-k capacitor dielectric layer formed directly on the highly doped fins. Contacts are electrically connected to the capacitor plates. A highly doped implantation layer having a conductivity type opposite to that of the highly doped region provides electrical isolation within the structure.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: May 14, 2019
    Assignee: International Business Machines Corporation
    Inventors: Keith E. Fogel, Pouya Hashemi, Shogo Mochizuki, Alexander Reznicek