Abstract: A device is provided, including: a first device package including: a first redistribution structure including a first redistribution line and a second redistribution line; a die on the first redistribution structure; a first via coupled to a first side of the first redistribution line; a second via coupled to a first side of the second redistribution line and extending through the second redistribution line; an encapsulant surrounding the die, the first via, and the second via; and a second redistribution structure over the encapsulant, the second redistribution structure electrically connected to the die, the first via, and the second via; a first conductive connector coupled to a second side of the first redistribution line, the first conductive connector disposed along a different axis than a longitudinal axis of the first via; and a second conductive connector coupled to a second side of the second redistribution line, the second conductive connector disposed along a longitudinal axis of the second via.

Abstract: A layout includes a plurality of cells and at least one dummy gate electrode continuously extends across the cells. Since the dummy gate electrode is electrically conductive, the dummy gate electrode can be utilized for interconnecting the cells. That is, some signals may travel through the dummy gate electrode rather than through a metal one line or a metal two line. Therefore, an amount of metal one lines and/or metal two lines for interconnecting the cells can be reduced.

Abstract: Implanting ions to form a cleave layer in a semiconductor device causes damage to sensitive materials such as high-K dielectrics. In a process for forming a cleave layer and repairing damage caused by ion implantation, ions are implanted through a circuit layer of a substrate to form a cleave plane. The substrate is exposed to a hydrogen gas mixture for a first time at a first temperature to repair damage caused by the implanted ions. A cleaving process may then be performed, and the cleaved substrate may be stacked in a 3DIC structure.

Abstract: A semiconductor package device comprises a substrate, a light emitter, a light detector and a transparent conductive film. The substrate as a first surface and a second surface opposite to the first surface. The light emitter is disposed on the first surface of the substrate and has a light emission area adjacent to the first surface of the substrate. The light detector is disposed on the first surface of the substrate and has a light receiving area adjacent to the first surface of the substrate. The transparent conducting film is disposed on the second surface of the substrate.

Abstract: A display device is provided. The display device includes a substrate having a surface including a display area and a non-display area adjacent to the display area; a plurality of light-emitting diodes disposed on the display area of the substrate, wherein the light-emitting diode includes a contact electrode; and an anisotropic conductive layer disposed between the substrate and the plurality of light-emitting diodes, wherein the anisotropic conductive layer has a cross-sectional sidewall profile, and at least a part of the cross-sectional sidewall profile of the anisotropic conductive layer is in a shape of curve.

Abstract: The disclosed technology generally relates to integrating semiconductor dies and more particularly to bonding semiconductor substrates. In an aspect, a method of bonding semiconductor substrates includes providing a first substrate and a second substrate. Each of the first substrate and the second substrate comprises a dielectric bonding layer comprising one or more a silicon carbon oxide (SiCO) layer, a silicon carbon nitride (SiCN) layer or a silicon carbide (SiC) layer. The method additionally includes, prior to bonding the first and second substrates, pre-treating each of the dielectric bonding layer of the first substrate and the dielectric bonding layer of the second substrate. Pre-treating includes a first plasma activation process in a plasma comprising an inert gas, a second plasma activation process in a plasma comprising oxygen, and a wet surface treatment including a water rinsing step or an exposure to a water-containing ambient.

Abstract: A self aligned via and a method for fabricated a semiconductor device using a double-trench constrained self alignment process to form the via. The method includes forming a first trench and depositing a first metal into the first trench. Afterwards, the process includes depositing a dielectric layer over the first metal such that a top surface of the dielectric layer is at substantially the same level as the top surface of the first trench. Next, a second trench is formed and a via is formed by etching the portion of the dielectric layer exposed by the overlapping region between the first trench and the second trench. The via exposes a portion of the first metal and a second metal is deposited into the second trench such that the second metal is electrically coupled to the first metal.

Abstract: An array substrate includes at least: a glass substrate on which a driver is mounted; a panel side output terminal disposed in a mounting area of the glass substrate and connected to the driver; a first terminal portion; a gate insulation film including a first contact hole at a position overlapping a first terminal portion; a second terminal portion disposed to overlap at least a first contact hole and an opening edge of the first contact hole; a first interlayer insulation film including a second contact hole at a position overlapping a second terminal portion not to overlap the first contact hole; and a third terminal portion disposed to overlap at least the second contact hole and an opening edge of the second contact hole.

Abstract: A display panel includes an array substrate, including a display region containing a plurality of display pixels and a border region; and a scattering layer, located on one side of the array substrate and including a scattering region. The plurality of display pixels includes a plurality of pixel rows extending along a first direction and a plurality of pixel columns extending along a second direction. The first direction and the second direction intersect each other. The border region includes an irregularly-shaped border. The plurality of display pixels includes a first plurality of display pixels adjacent to the irregularly-shaped border. The first plurality of display pixels is located in different pixel rows and different pixel columns. A plurality of scattering particles is disposed in the scattering region, and an orthogonal projection of the scattering region on the array substrate covers at least a portion of the first plurality of display pixels.

Abstract: A display device for preventing a damage of an electrode contact portion is disclosed. The display device includes a display area, on which an organic light emitting diode including a first electrode, an organic layer, and a second electrode is positioned, and a non-display area positioned outside the display area. The non-display area includes an electrode contact portion in which the second electrode and a low potential voltage line are connected to each other through at least one connection pattern. The electrode contact portion includes a passivation layer including a plurality of passivation holes exposing the at least one connection pattern, and an overcoat layer including an overcoat hole exposing the passivation layer.

Abstract: To restrain a side portion of a trench from being damaged by ion implantation. A method for manufacturing a semiconductor device comprises a stacking process, an ion implantation process, a heat treatment process, a groove forming process, and a first electrode forming process. In the stacking process, a p-type semiconductor layer is stacked on a first n-type semiconductor layer. In the ion implantation process, an n-type impurity or a p-type impurity is ion-implanted into a position on a surface of the p-type semiconductor layer. The position is away from a position where a groove is to be formed. In the heat treatment process, heat treatment is performed to activate the ion-implanted impurity so as to form an implanted region and to diffuse a p-type impurity in the p-type semiconductor layer into the first n-type semiconductor layer located below the implanted region so as to form a p-type impurity diffused region.

Abstract: A package includes a first electrode and a second electrode that are located at a bottom portion of a bottomed recess, and a first resin securing the first electrode and the second electrode in place and forming a part of the bottomed recess. The first electrode has a first outer lead having a first indentation at a tip in a plan view. The second electrode has a second outer lead having a second indentation at a tip in a plan view. The first resin has at least a portion between the first electrode and the second electrode located at the bottom portion of the bottomed recess, wall portions structuring lateral walls of the bottomed recess, and flange portions having the same thickness as a thickness of the first outer lead and different outward widths from the wall portions on both sides of the first outer lead in a plan view.

Abstract: A method of forming an electronic device structure includes providing an electronic component having a first major surface, an opposing second major surface, a first edge surface, and an opposing second edge surface. A substrate having a substrate first major surface and an opposing substrate second major surface is provided. The second major surface of the first electronic component is placed proximate to the substrate first major surface and providing a conductive material adjacent the first edge surface of the first electronic component. The conductive material is exposed to an elevated temperature to reflow the conductive material to raise the first electronic component into an upright position such that the second edge surface is spaced further away from the substrate first major surface than the first edge surface. The method is suitable for providing electronic components, such as antenna, sensors, or optical devices in a vertical or on-edge.

Abstract: A method of forming a device includes providing a first substrate having a first area and a second area, forming a range compensating material over the first substrate so that the first material is disposed over the first area and not disposed over the second area, implanting ions into the first area and the second area to form first and second cleave planes at first and second depths, respectively, each of the first and second cleave planes being defined by a concentration of the implanted ions, removing the range compensating material, and cleaving the first substrate along a cleave profile including the first and second cleave planes.

Abstract: Semiconductor memory cells, array and methods of operating are disclosed. In one instance, a memory cell includes a bi-stable floating body transistor and an access device; wherein the bi-stable floating body transistor and the access device are electrically connected in series.

Abstract: The present invention provides an organic light-emitting diode display panel including a substrate, a thin film transistor arranged on the substrate, a planarization layer arranged on the substrate, a first touch electrode arranged on a surface of the planarization layer, an electrode insulation layer arranged on the surface of the planarization layer, a metal anode arranged on a surface of the electrode insulation layer and electrically connected to the source electrode or the drain electrode of the thin film transistor, and, a second touch electrode arranged on the surface of the electrode insulation layer and electrically connected to the first touch electrode.

Abstract: A light emitting diode device with flip-chip structure includes a transparent protective substrate, a transparent conductor layer, a glue layer, a group III-V stack layer, a first conductivity metal electrode, a second conductivity metal electrode and an insulating layer. The transparent conductor layer is formed on the transparent protective substrate. The glue layer bonds the transparent protective substrate and the transparent conductor layer. The group III-V stack layer and the first conductivity metal electrode are respectively formed on a first portion and a second portion of the transparent conductor layer. The second conductivity metal electrode is formed on a portion of the group III-V stack layer. The insulating layer covers exposed portions of the transparent conductor layer and the group III-V stack layer, and the insulating layer further covers portions of the first and second conductivity metal electrodes, so as to expose the first and second conductivity metal electrodes.

Abstract: Processing methods to create self-aligned contacts are described. A conformal liner can be deposited in a feature in a substrate surface leaving a gap between the walls of the liner. A tungsten film can be deposited in the gap of the liner and volumetrically expanded. The expanded film can be removed and replaced with a contact material to a make a contact. In some embodiments, a conformal tungsten film can be formed in the feature leaving a gap between the walls. A dielectric can be deposited in the gap and the conformal tungsten film can be volumetrically expanded to grow two pillars. The pillars can be removed and replaced with a contact material to make two contacts.

Abstract: A method of forming a superconductor interconnect structure is disclosed. The method includes forming a dielectric layer overlying a substrate, forming an interconnect opening in the dielectric layer, and moving the substrate to a deposition chamber. The method further includes depositing a superconducting metal in the interconnect opening, by performing a series of superconducting deposition and cooling processes to maintain a chamber temperature at or below a predetermined temperature until the superconducting metal has a desired thickness, to form a superconducting element in the superconductor interconnect structure.

Abstract: An etch back air gap (EBAG) process is provided. The EBAG process includes forming an initial structure that includes a dielectric layer disposed on a substrate and a liner disposed to line a trench defined in the dielectric layer. The process further includes impregnating a metallic interconnect material with dopant materials, filling a remainder of the trench with the impregnated metallic interconnect materials to form an intermediate structure and drive-out annealing of the intermediate structure. The drive-out annealing of the intermediate structure serves to drive the dopant materials out of the impregnated metallic interconnect materials and thereby forms a chemical- and plasma-attack immune material.