Abstract: Micro pick-and-bond heads, assembly methods, and device assemblies. In, embodiments, micro pick-and-bond heads transfer micro device elements, such as (micro) LEDs, en masse from a source substrate to a target substrate, such as a LED display substrate. Anchor and release structures on the source substrate enable device elements to be separated from a source substrate, while pressure sensitive adhesive (PSA) enables device elements to be temporarily affixed to pedestals of a micro pick-and-bond head. Once the device elements are permanently affixed to a target substrate, the PSA interface may be defeated through peeling and/or thermal decomposition of an interface layer.

Abstract: The device according to the invention comprises a nanostructured LED with a first group of nanowires protruding from a first area of a substrate and a contacting means in a second area of the substrate. Each nanowire of the first group of nanowires comprises a p-i-n-junction and a top portion of each nanowire or at least one selection of nanowires is covered with a light-reflecting contact layer. The contacting means of the second area is in electrical contact with the bottom of the nanowires, the light-reflecting contact layer being in electrical contact with the contacting means of the second area via the p-i-n-junction. Thus when a voltage is applied between the contacting means of the second area and the light-reflecting contact layer, light is generated within the nanowire. On top of the light-reflecting contact layer, a first group of contact pads for flip-chip bonding can be provided, distributed and separated to equalize the voltage across the layer to reduce the average serial resistance.

Abstract: An organic light emitting diode display panel includes data lines arranged in a first direction; gate lines arranged in a second direction to cross the data lines; a driving voltage line arranged in the first direction; a reference voltage line arranged in the first direction; data pads respectively at ends of corresponding ones of the data lines; a driving voltage pad at an end of the driving voltage line; and a reference voltage pad at an end of the reference voltage line. A first distance is defined between the driving voltage pad and an adjacent data pad, a second distance is defined between adjacent ones of the data pads, and a third distance is defined between the reference voltage pad and an adjacent data pad. At least two of the first distance, the second distance, and the third distance are different from each other.

Abstract: Micro pick-and-bond heads, assembly methods, and device assemblies. In, embodiments, micro pick-and-bond heads transfer micro device elements, such as (micro) LEDs, en masse from a source substrate to a target substrate, such as a LED display substrate. Anchor and release structures on the source substrate enable device elements to be separated from a source substrate, while pressure sensitive adhesive (PSA) enables device elements to be temporarily affixed to pedestals of a micro pick-and-bond head. Once the device elements are permanently affixed to a target substrate, the PSA interface may be defeated through peeling and/or thermal decomposition of an interface layer.

Abstract: Disclosed is an organic electroluminescent display panel, a method for manufacturing the same and a display apparatus. The organic electroluminescent display panel comprises a plurality of luminescent units, wherein light-isolating members are disposed between the plurality of luminescent units for isolating light emitted from the respective luminescent units. Therefore, the organic electroluminescent display panel, the method for manufacturing the same and the display apparatus according to the present invention can prevent mutual interference between the light from the respective luminescent units of the organic electroluminescent display panel.

Abstract: A semiconductor substrate (1) includes a region (AR3) between a region (AR1) and a region (AR2), a control gate electrode (CG) is formed on an upper surface (TS1) of the region (AR1), and a memory gate electrode (MG) is formed on an upper surface (TS2) of the region (AR2). The upper surface (TS2) is lower than the upper surface (TS1), and the region (AR3) has a connection surface (TS3) connecting the upper surface (TS1) and the upper surface (TS2). An end (EP1) of the connection surface (TS3) which is on the upper surface (TS2) side is arranged closer to the memory gate electrode (MG) than an end (EP2) of the connection surface (TS3) which is on the upper surface (TS1) side, and is arranged lower than the end (EP2).

Abstract: The present disclosure provides a top-emitting white organic light emitting diode (OLED) device, a method for manufacturing the same and a display apparatus. The OLED device includes a plurality of pixel units on a substrate, wherein each pixel unit includes a first electrode layer, an organic layer and a second electrode layer arranged subsequently on the substrate from bottom up, and the organic layer in each pixel unit includes a gradually-varied cavity length, and the gradually-varied cavity length corresponds to a range from a wavelength of red light to a wavelength of blue light.

Abstract: An electrical device that includes at least two active wafers having at least one through silicon via, and at least one unitary electrical communication and spacer structure present between a set of adjacently stacked active wafers of the at least two active wafers. The unitary electrical communication and spacer structure including an electrically conductive material core providing electrical communication to the at least one through silicon via structure in the set of adjacently stacked active wafers and a substrate material outer layer. The at least one unitary electrical communication and spacer structure being separate from and engaged to the adjacently stacked active wafers, wherein coolant passages are defined between surfaces of the adjacently stacked active wafers and the at least one unitary electrical communication and spacer structure.

Abstract: A chip package including a first substrate is provided. The first substrate includes a sensing device. A second substrate is attached onto the first substrate and includes an integrated circuit device. A first conductive structure is electrically connected to the sensing device and the integrated circuit device through a redistribution layer disposed on the first substrate. An insulating layer covers the first substrate, the second substrate and the redistribution layer. The insulating layer has a hole therein and a second conductive structure is disposed under the bottom of the hole. A method for forming the chip package is also provided.

Abstract: High integrity, lower power consuming semiconductor devices and methods for manufacturing the same. The semiconductor device includes: semiconductor substrate; a well region in the semiconductor substrate; an interlayer structure over the well region, the interlayer structure including a back gate conductor, semiconductor fins at both sides of the back gate conductor and respective back gate dielectric isolating the back gate conductor from the semiconductor fins, respectively, wherein the well region functions as one portion of a conductive path of the back gate conductor; a punch-through stop layer at a lower portion of the semiconductor fin; a front gate stack intersecting the semiconductor fin, the front gate stack including a front gate dielectric and a front gate conductor and the front gate dielectric isolating the front gate conductor from the semiconductor fin; and a source region and a drain region connected to a channel region provided by the semiconductor fin.

Abstract: An organic light-emitting display apparatus includes a first substrate corresponding to a display area and a periphery area, a second substrate facing the first substrate, a first metal layer at the periphery area of the first substrate, and defining a plurality of first holes, a second metal layer on the first metal layer, and defining a plurality of second holes that are differently sized than the first holes, a third metal layer on the second metal layer, and defining a plurality of third holes that are differently sized than the second holes, and a sealing member bonding the first substrate and the second substrate, and filling a partial region of the first, second, and third holes.

Abstract: A light emitting device of the invention includes a substrate; a light emitting element mounted on the upper surface of the substrate; a wire that is electrically connected to the light emitting element; and a plate-shaped light-transmissive member that covers the light emitting element. The wire has a stack structure in which a first bonding ball, a bonding wire, and a second bonding ball are stacked in that order, the stack structure is disposed on the upper surface of the light emitting element, and the plate-shaped light-transmissive member is disposed above the stack structure.

Abstract: Embodiments of a packaged semiconductor device with interior polygon pads are disclosed. One embodiment includes a semiconductor chip and a package structure defining a rectangular boundary and having a bottom surface that includes interior polygonal pads exposed at the bottom surface of the package structure and located on a centerline of the bottom surface of the package structure and edge polygonal pads exposed at the bottom surface of the package structure, located at an edge of the rectangular boundary, and including one edge polygonal pad in the vicinity of each corner of the rectangular boundary. The interior polygonal pads are configured such that a line running between at least one vertex of each of the interior polygonal pads is parallel to an edge of the rectangular boundary of the package structure.

Abstract: The performances of a semiconductor device are improved. A semiconductor device has a photodiode and a transfer transistor formed in a pixel region. Further, the semiconductor device has a second transistor formed in a peripheral circuit region. The transfer transistor includes a first gate electrode, and a film part formed of a thick hard mask film formed over the first gate electrode. The second transistor includes a second gate electrode, source/drain regions, silicide layers formed at the upper surface of the second gate electrode, and the upper surfaces of the source/drain regions.

Abstract: One or more cross-wafer capacitors are formed in an electronic component, circuit, or device that includes stacked wafers. One example of such a device is a stacked image sensor. The image sensor can include two or more wafers, with two wafers that are bonded to each other each including a conductive segment adjacent to, proximate, or abutting a bonding surface of the respective wafer. The conductive segments are positioned relative to each other such that each conductive element forms a plate of a capacitor. A cross-wafer capacitor is formed when the two wafers are attached to each other.

Abstract: A field-effect transistor includes a substrate; a source electrode, a drain electrode, and a gate electrode that are formed on the substrate; a semiconductor layer by which a channel is formed between the source electrode and the drain electrode when a predetermined voltage is applied to the gate electrode; and a gate insulating layer provided between the gate electrode and the semiconductor layer. The gate insulating layer is formed of an amorphous composite metal oxide insulating film including one or two or more alkaline-earth metal elements and one or two or more elements selected from a group consisting of Ga, Sc, Y, and lanthanoid except Ce.

Abstract: According to an exemplary embodiment, a method of forming a vertical structure is provided. The method includes the following operations: providing a substrate; providing the vertical structure with a source and a channel over the substrate; forming a spacer over the vertical structure; etching a portion of the spacer to expose the source; forming a first metal layer over the vertical structure; and thermal annealing the first metal layer to form a bottom silicide penetrating the source; and substantially removing the spacer.

Abstract: An organic light emitting display device includes: a substrate; a semiconductor on the substrate and including a switching channel of a switching transistor and a driving channel of a driving transistor, wherein the switching transistor and the driving transistor are spaced; a first insulating layer covering the semiconductor; a switching gate electrode on the first insulating layer and overlapped with the switching channel and a driving gate electrode on the first insulating layer and overlapped with the driving channel; a second insulating layer covering the switching gate electrode and the driving gate electrode; a data line on the second insulating layer and configured to transmit a data signal, a driving voltage line on the second insulating layer and configured to transmit a driving voltage; a passivation layer; a pixel electrode on the passivation layer; and a pixel connecting member on the passivation layer.

Abstract: A FET type gas-sensitive device has a floating electrode formed in a horizontal direction. The device achieves noise reduction, process simplification, pollution control, sensing speed improvement, various sensing material applicability and mechanical stability etc. in comparison with a gas-sensitive device that is vertically stacked with a floating electrode, a sensing material layer and a control electrode. The device can be assembled easily with a plurality of gas-sensitive devices being operated by various sensing mechanisms in one substrate.

Abstract: The disclosure relates to organic field effect transistors, and methods for producing organic field effect transistors. The organic field effect transistors may include a first electrode, and a second electrode, the electrodes providing a source electrode and a drain electrode, an intrinsic organic semiconducting layer in electrical contact with the first and second electrode, a gate electrode, a gate insulator provided between the gate electrode and the intrinsic organic semiconducting layer, and a doped organic semiconducting layer including an organic matrix material and an organic dopant.