Abstract: The present invention provides a dry etching method for achieving a satisfactory anisotropic etching of, for example, a semiconductor wafer, particularly, a polysilicon layer formed on the wafer. In the present invention, a mixed gas comprising a first gas containing Br and a second gas containing a halogen element other than Br, e.g., a mixed gas consisting of a HBr gas and a HCl gas, is introduced into a vacuum chamber. The mixed gas is converted into plasma by applying a high frequency power to an upper electrode 5. The plasma region is irradiated, as desired, with an ultraviolet light. The semiconductor wafer is etched with the plasma. The etching is carried out under optimum conditions. For example, the surface temperature of the semiconductor wafer, i.e., workpiece, is maintained at a level falling within a range of between 70.degree. C. and 120.degree. C. Also, the flow rate ratio of the mixed gas is suitably controlled.

Abstract: In a multi-level wiring structure of an IC device, an intermediate insulating layer on a portion of a field insulating layer where wiring layers are absent thereabove is selectively removed so that a gas gap is formed between lower wiring layers.

Abstract: A method of forming metal contact terminals (35) of a determined size having an insulating substrate (17) with a metal land (18) formed thereon and a passivating layer (19) provided with an opening exposing a part of the metal land by forming intermediate metal contact pad (33') in the contact opening, applying and patterning a photoresist, delineating the intermediate metal contact pad (33') using pattern (31) as an in-situ mask, depositing a lead-tin solder layer (34') over a metal mask to form a solder bump (34') on the final metal contact pad, and reflowing the solder to form a solder ball (34). Thereby achieving the metal contact terminal (35) at the contact pad site. The above method has applicability to the fabrication of contact terminals for high density/high count I/O connections for advanced semiconductor chips that are appropriate for flip-chip (C4) or face-down bonding thereof on metallized ceramic (MC) substrates.

Abstract: A method of manufacturing wiring layers of semiconductor devices in which a base layer made of electroconductive material is formed on a wiring-intended area of the substrate surface and an insulating layer is formed on the area other than the wiring intended area. Then the wiring layer is grown on the base layer up to substantially the same level as that of the insulating layer up, hereby planarity of the surfaces of the device is maintained after wiring formation.

Abstract: A planar electrical interconnection system suitable for an integrated circuit is created by a process in which an insulating layer (31) having a planar upper surface is formed on a substructure after which openings (32) are etched through the insulating layer. A conductive planarizing layer (33) having a planar upper surface is formed on the insulating layer and in the openings by an operation involving isotropic deposition of a material, preferably tungsten, to create at least a portion of the planarizing layer extending from its upper surface partway into the openings. The planarizing layer is then etched down to the insulating layer. Consequently, its upper surface is coplanar with that of the material (33') in the openings. The foregoing steps are repeated to create another coplanar conductive/insulating layer (34 and 36'). If the lower openings are vias while the upper openings are grooves, the result is a planar interconnect level. Further planar interconnect levels can be formed in the same way.

Abstract: An interconnect (16',18', 18"), whose interlevel contacts comprise refractory (10) to refractory or refractory to semiconductor substrate (13) interfaces, comprises patterned refractory core portions (10), consisting of tungsten or molybdenum, having top portions (10a) and opposed side portions (10b), provided with sidewall spacers (32a) of aluminum, gold or copper or alloys thereof and formed on surfaces (12a) of insulating layers (12). The sidewall spacers afford lateral low resistivity cladding of the refractory portions as well as suppression of the electromigration failure modes of voiding and whiskering, while leaving the top portion of the core portions available for refractory to refractory contacts and the bottom portion of the core portions available for refractory to refractory or refractory to silicon contacts.

Abstract: A stable, low resistance contact is formed in a contact hole (16) through an insulating layer (14), e.g., silicon dioxide, formed on a surface of a semiconductor substrate (12), e.g., silicon, to a portion of a doped region (10) in said semiconductor surface. The contact comprises (a) an adhesion and contacting layer (18) of titanium formed along the walls of the insulating layer and in contact with the portion of the doped region; (b) a barrier layer (20) formed over the adhesion and contacting layer; and (c) a conductive material (22) formed over the barrier layer and at least substantially filling said contact hole. A patterned metal layer (26) forms an ohmic contact interconnect to other devices and external circuitry.The adhesion and contacting layer and barrier layer are either physically or chemically vapor deposited onto the oxide surface. The conductive layer comprises one of CVD or bias sputtered tungsten, molybdenum or in situ doped CVD polysilicon.

Abstract: A silicon-over-insulator transistor is provided having a semiconductor mesa (40) overlying a buried oxide (42). Insulating regions (50) are formed at the sides of the semiconductor mesa (40). An oxidizable layer (56) is formed over the mesa's insulating region (46). This oxidizable layer (56) is then anisotropically etched, resulting in oxidizable sidewalls (60). An optional foot (70) may be formed at the bottom edge of the oxidizable sidewalls (76). These oxidizable sidewalls (76) are then oxidized, resulting in a pure oxide sidewall (64). The gate (66) is then formed over the pure oxide sidewalls (64) and a gate oxide (62).

Abstract: A substrate structure for a composite semiconductor device comprises first and second semiconductor substrates whose major surfaces are bonded to each other with an insulating layer interposed therebetween. In this substrate structure, an epitaxial layer is grown from part of the second semiconductor substrate, forming one element area, and another element area is formed in the first semiconductor substrate area and isolated from the epitaxial layer.

Abstract: Disclosed is a method of forming a uniform length gate electrode and contact for a microwave field-effect transistor where the gate electrode has a length of less than one micron. A photoresist plug is formed on the surface of a first photoresist layer, the plug functioning as a shadow mask in the subsequent deposition of a plasma-etch-resistant material (aluminum) over the surface of the plug and the first photoresist layer. A third photoresist layer is formed over the device structure whereby a contact region can be formed on the surface of the semiconductor sub-strate adjacent to the device region. Subsequently, the third photoresist layer is removed, and the previously shielded photoresist material over the gate electrode location is removed by plasma etch using the metal-covered plug and metal-covered first photoresist layer as a plasma-etch shield.

Abstract: A process is disclosed for making a self-aligned metal (preferably tungsten) connection in an integrated circuit. A contact hole formed in a first dielectric layer on a substrate is filled with metal, after which the first dielectric layer and the metal-filled contact hole are covered with a second dielectric layer. A photoresist layer is formed over the second dielectric layer and is patterned. A trench is formed in the exposed second dielectric layer and a thin layer of silicon or a metal such as tungsten is then sputtered or evaporated to form a layer of the silicon or metal on the upper surface of the patterned photoresist and the bottom and side walls of the trench. The patterned photoresist is removed and the trench is filled with metal.

Abstract: A semiconductor wafer on which silicon or the like is epitaxially grown and p-type or n-type impurities are doped and which has at the rear surface except for the peripheral edge portion thereof a blocking film for preventing jumping out of impurities therefrom which causes auto-doping, thereby preventing silicon particles from being produced at the peripheral surface and preventing the semiconductor wafer from being contaminated by the silicon particles during the manufacturing of a semiconductor device.

Abstract: A semiconductor body is treated by providing a layer of dielectric material over a peripheral region of the front face of the body, mounting the body on a support member with the front face of the body in confronting relationship with the support member, and removing material of the body in the peripheral region, so as to expose at least a portion of the layer of dielectric material. A layer of metal is formed on the back face of the body and is connected to an electrical terminal.

Abstract: A method of fabricating a semiconductor device in an integrated circuit. A conductive titanium layer is deposited on a substrate in which source, drain and gate regions have been created. A titanium nitride layer is applied as a cap over the titanium layer. A first anneal at a relatively low temperature is performed, causing portions of the titanium which are adjacent the silicon surface to form a titanium-silicon compound and causing the remaining titanium and titanium nitride to form a nitride coating. This nitride coating is etched away and a final high-temperature anneal is performed, resulting in thick, smooth titanium silicide (TiSi.sub.2) layers on the source and drain regions and gate pads.