Patents Examined by Laura N. Schillinger
  • Patent number: 6156590
    Abstract: In producing TFT by crystallizing an amorphous silicon film by the action of nickel, the influence of nickel on the TFT produced is inhibited. A mask 104 is formed over an amorphous silicon film 102, and a nickel-containing solution is applied thereover. In that condition, nickel is kept in contact with the surface of the amorphous silicon film at the opening 103 of the mask. Then, this is heated to crystallize the amorphous silicon film. Next, a phosphorus-containing solution is applied thereto, so that phosphorus is introduced into the silicon film in the region of the opening 103. This is again heated, whereby nickel is gettered in the region into which phosphorus has been introduced. In this process, the nickel concentration in the silicon film is reduced.
    Type: Grant
    Filed: June 16, 1998
    Date of Patent: December 5, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Hideto Ohnuma
  • Patent number: 6150670
    Abstract: A process for fabricating a gate oxide of a vertical transistor. In a first step, a trench is formed in a substrate, the trench extending from a top surface of the substrate and having a trench bottom and a trench side wall. The trench side wall comprises a <100> crystal plane and a <110> crystal plane. Next, a sacrificial layer having a uniform thickness is formed on the trench side wall. Following formation of the sacrificial layer, nitrogen ions are implanted through the sacrificial layer such that the nitrogen ions are implanted into the <110> crystal plane of the trench side wall, but not into the <100> crystal plane of the trench side wall. The sacrificial layer is then removed and the trench side wall is oxidized to form the gate oxide.
    Type: Grant
    Filed: November 30, 1999
    Date of Patent: November 21, 2000
    Assignees: International Business Machines Corporation, Infineon Technologies North America Corp.
    Inventors: Johnathan E. Faltermeier, Ulrike Gruening, Suryanarayan G. Hegde, Rajarao Jammy, Brian S. Lee, Helmut H. Tews
  • Patent number: 6071751
    Abstract: Channel-hot-carrier reliability can be improved by deuterium sintering. However, the benefits obtained by deuterium sintering can be greatly reduced or destroyed by thermal processing steps which break Si--H and Si--D bonds. A solution is to increase the deuterium concentration near the interface to avoid subsequent depletion of deuterium due to diffusion. By using a rapid quench of a sintered wafer, the deuterium concentration near the interface is increased, because the rapid quench impedes the ability of the deuterium to diffuse away from the gate oxide interface.
    Type: Grant
    Filed: July 28, 1998
    Date of Patent: June 6, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Robert M. Wallace, Kenneth C. Harvey