Abstract: An aspect of the invention includes a method for forming a contact in a dielectric layer over a semiconductor substrate. The method may comprise: forming a contact opening in a dielectric layer over the semiconductor substrate to expose an upper portion of the semiconductor substrate; depositing a first liner layer to conformally coat the contact opening; causing a portion of the first liner layer to diffuse into the upper portion of the semiconductor substrate to form a first intermix region at the upper portion of the semiconductor substrate; depositing a refractory metal layer over the first intermix region; and depositing a metal in the contact opening thereby forming the contact.

Abstract: A light emitting element includes a semiconductor including an active layer, and a planar shape of the light emitting elements including a concave polygon. The planar shape of the concave polygon has interior angles including at least one acute angle.

Abstract: A grid connector for communicating with a printed memory includes a substrate and a plurality of first conductive pads coupled to the substrate. Each of the first conductive pads protrudes outward with respect to an outer surface of the substrate. A subset of the first conductive pads is configured to contact a second conductive pad of the printed memory, regardless of an orientation of the printed memory with respect to the grid connector as long as the second conductive pad is within a boundary of the first conductive pads.

Abstract: A high voltage (HV) transistor is integrated on a silicon-on-insulator (SOI) substrate. The HV transistor is disposed in a HV device region disposed on a bulk substrate of the SOI substrate. The HV device region includes a top field oxide which includes at least a part of a buried oxide (BOX) of the SOI substrate. A HV gate is disposed in HV region overlapping the HV top field oxide and includes first and second HV gate sidewalls. A drain is disposed on the bulk substrate and displaced from the first HV gate sidewall by the HV top field oxide. A source is disposed on the bulk substrate adjacent to the side of the second HV gate sidewall.

Abstract: A symmetrical lateral bipolar junction transistor (SLBJT) is provided. The SLBJT includes a p-type semiconductor substrate, a n-type well, an emitter of a SLBJT situated in the n-type well, a base of the SLBJT situated in the n-type well and spaced from the emitter by a distance on one side of the base, a collector of the SLBJT situated in the n-type well and spaced from the base by the distance on an opposite side of the base, and an electrical connection to the substrate outside the n-type well. The SLBJT is used to characterize a transistor in a circuit by electrically coupling the SLBJT to a gate of the test transistor, applying a voltage to the gate, and characterizing aspect(s) of the test transistor under the applied voltage. The SLBJT protects the gate against damage to the gate dielectric.

Abstract: A method for fabricating a photosensor array integrated circuit includes forming an isolation trench by a method comprising depositing a hard mask layer on a [110]-oriented single-crystal silicon substrate wafer, depositing, exposing, and developing a photoresist on the hard mask layer to define photoresist openings of locations for the trenches, dry plasma etching through the photoresist openings to form openings in the hard mask layer of locations for the trenches, and performing an anisotropic wet etch through the openings in the hard mask layer. In particular embodiments, the trenches are lined with P-type silicon, a silicon dioxide dielectric, and an additional oxide layer before being filled with tungsten.

Abstract: A single photon avalanche diode (SPAD) image sensor is disclosed. The SPAD image sensor includes: a substrate having a front surface and a back surface; a trench isolation in the substrate, the trench isolation extending from the front surface of the substrate toward the back surface of the substrate, the trench isolation having a first surface and a second surface opposite to the first surface, the first surface being coplanar with the front surface of the substrate, the second surface being distanced from the back surface of the substrate by a distance greater than 0; wherein the substrate includes: a first layer doped with dopants of a first conductivity type, the first layer extending from the back surface of the substrate toward the trench isolation and laterally surrounding at least a portion of sidewalls of the trench isolation.

Abstract: A method includes forming a first directed self-assembly material above a substrate. The substrate is patterned using the first directed self-assembly material to define at least one fin in the semiconductor substrate. A second directed self-assembly material is formed above the at least one fin to expose a top surface of the at least one fin. A substantially vertical nanowire is formed on the top surface of the at least one fin. At least a first dimension of the vertical nanowire is defined by an intrinsic pitch of the first directed self-assembly material and a second dimension of the vertical nanowire is defined by an intrinsic pitch of the second directed self-assembly material.