Abstract: A method for recording a duration of use of a data block is disclosed, as well as a data storage device implementing that method. The data block is either an in-use data block or an empty data block. The method includes steps of: receiving and writing data into one of the in-use data blocks and writing a program time and a time interval of the data into the in-use data block. Wherein the time interval is a difference between the program time and an initial program time of the in-use data block, and the initial program time was recorded when the in-use data block wrote a first piece of data.

Abstract: Disclosed approaches for managing a translation look-aside buffer (TLB) have a bus master circuit that issues a read request that specifies a first virtual address of a first page. In response to a sequential access being identified and before data of the first page is returned, the bus master circuit issues a dummy read request that specifies a second virtual address of a second page. A TLB has mappings of virtual addresses to physical addresses, and a translation logic circuit translates virtual addresses to physical addresses. The translation logic circuit signals a miss in response to absence of a virtual address in the TLB. A control circuit in the MMU determines from a page table a mapping of a virtual address to a physical address in response to the signaled miss. The translation logic circuit updates the TLB circuit with the mapping.

Abstract: A computer readable storage medium embodies program instructions executable by a processor to perform a method including identifying a product warranty for each of a plurality of flash memory devices within a system, wherein the product warranty includes a maximum number of writes and a maximum age, and tracking the number of writes and the age of each flash memory device. The method further includes determining, for each flash memory device, a number of pro rata writes remaining in the product warranty, which is determined as a number of writes remaining until the flash memory device reaches the maximum number of writes divided by an amount of time remaining until the flash memory reaches the maximum age. The method then causes data to be written to the flash memory device having the greatest number of pro rata writes remaining in the product warranty.

Abstract: One of a plurality of chip select inputs of a load-reduced dual inline memory module (LRDIMM) may be repurposed to an address input. One of a plurality of memory ranks of the LRDIMM may be selected based on a remainder of the plurality of chip select inputs. The repurposed chip select input may be used to support non-binary rank multiplication of the LRDIMM.

Abstract: Digital signal processors often operate on two operands per instruction, and it is desirable to retrieve both operands in one cycle. Some data caches connect to the processor over two busses and internally uses two or more memory banks to store cache lines. The allocation of cache lines to specific banks is based on the address that the cache line is associated. When two memory accesses map to the same memory bank, fetching the operands incurs extra latency because the accesses are serialized. An improved bank organization for providing conflict-free dual-data cache access—a bus-based data cache system having two data buses and two memory banks—is disclosed. Each memory bank works as a default memory bank for the corresponding data bus. As long as the two values of data being accessed belong to two separate data sets assigned to the two respective data buses, memory bank conflicts are avoided.

Abstract: Embodiments are described for repairing the locality of a namespace index on a deduplication storage device. A namespace index is selected from a plurality of namespace indices, each of which is mountable on the storage system. The selected namespace index is traversed and divided into regions, each of which was stored in one or more storage containers. Locality information for each region is generated, including a density metric and a distribution metric. If either metric is below a threshold value for the metric, then the region is enqueued for namespace locality repair. A region can be repaired by reading the region into memory and flushing the memory to co-located containers on the storage system.

Abstract: In response to a determination to allocate additional storage, within a real address space employed by a system memory of a data processing system, for translation control entries (TCEs) that translate addresses from an input/output (I/O) address space to the real address space, a determination is made whether or not a first real address range contiguous with an existing TCE data structure is available for allocation. In response to determining that the first real address range is available for allocation, the first real address range is allocated for storage of TCEs, and a number of levels in the TCE data structure is retained. In response to determining that the first real address range is not available for allocation, a second real address range discontiguous with the existing TCE data structure is allocated for storage of the TCEs, and a number of levels in the TCE data structure is increased.

Abstract: In response to a determination to allocate additional storage, within a real address space employed by a system memory of a data processing system, for translation control entries (TCEs) that translate addresses from an input/output (I/O) address space to the real address space, a determination is made whether or not a first real address range contiguous with an existing TCE data structure is available for allocation. In response to determining that the first real address range is available for allocation, the first real address range is allocated for storage of TCEs, and a number of levels in the TCE data structure is retained. In response to determining that the first real address range is not available for allocation, a second real address range discontiguous with the existing TCE data structure is allocated for storage of the TCEs, and a number of levels in the TCE data structure is increased.

Abstract: Embodiments disclose techniques for enabling a guest operating system (OS) to directly invalidate entries in a translation lookaside buffer (TLB). In one embodiment, the guest OS receives one or more invalidation credits for invalidating translation entries in a translation lookaside buffer (TLB) from a hypervisor. The guest OS decrements one invalidation credit from the one or more invalidation credits after invalidating a translation entry in the TLB. Upon determining that there are no remaining invalidation credits, the guest OS requests additional invalidation credits from the hypervisor. The hypervisor may choose to allocate the additional invalidation credits, based upon a determination of whether or not the guest OS is a rogue OS that poses a threat or risk to other guest OS in a computing system.

Abstract: Managing memory allocations in a computer system may include tagging a class of data structures with a tag that identities a longer memory-allocation time for objects that correspond to the class. In response to a memory-allocation request for an object, whether or not the object is associated with the tag can be determined through the class. If the object is not associated with the tag, memory can be allocated for the object from a first memory-allocation area that corresponds to a shorter memory-allocation time, and if the object is associated with the tag, memory can be allocated for the object from a second memory-allocation area that corresponds to the longer memory-allocation time.

Abstract: Systems and methods for providing dynamic processor topology information to a virtual machine hosted by a multi-processor computer system supporting non-uniform memory access (NUMA). An example method may comprise assigning a unique identifier to a virtual processor, determining that the virtual processor has been moved from a first physical processor to a second physical processor, determining a memory access latency value for the second physical processor, and updating an element of a data structure storing memory access latency information with the memory access latency value of the second physical processor, the element identified by the unique identifier of the virtual processor.

Abstract: Allocating distributed data structures and managing allocation of a symmetric heap can include defining, using a processor, the symmetric heap. The symmetric heap includes a symmetric partition for each process of a partitioned global address space (PGAS) system. Each symmetric partition of the symmetric heap begins at a same starting virtual memory address and has a same global symmetric break. One process of a plurality of processes of the PGAS system is configured as an allocator process that controls allocation of blocks of memory for each symmetric partition of the symmetric heap. Using the processor executing the allocator process, isomorphic fragmentation among the symmetric partitions of the symmetric heap is maintained.

Abstract: Allocating distributed data structures and managing allocation of a symmetric heap can include defining, using a processor, the symmetric heap. The symmetric heap includes a symmetric partition for each process of a partitioned global address space (PGAS) system. Each symmetric partition of the symmetric heap begins at a same starting virtual memory address and has a same global symmetric break. One process of a plurality of processes of the PGAS system is configured as an allocator process that controls allocation of blocks of memory for each symmetric partition of the symmetric heap. Using the processor executing the allocator process, isomorphic fragmentation among the symmetric partitions of the symmetric heap is maintained.

Abstract: Systems and methods for providing dynamic topology information to virtual machines hosted by a multi-processor computer system supporting non-uniform memory access (NUMA). An example method may comprise assigning, by a hypervisor executing on a computer system, unique identifiers to a plurality of memory blocks residing on a plurality of physical nodes; determining that a memory block has been moved from a first physical node to a second physical node; determining memory access latency values to the second physical node by a plurality of virtual processors of the computer system; and updating, using a unique identifier of the memory block, a data structure storing memory access latency information, with the memory access latency values for the memory block.

Abstract: A data storage system is disclosed that utilizes garbage collection and logs for managing system data. In one embodiment, system data stored in a non-volatile memory is updated based on the character of changes to data stored in a data storage system (e.g., changes caused by host system activity). For example, when changes to stored data are scattered (e.g., changes are made to random memory locations), it may be beneficial to generate and accumulate more logs reflecting changes to the system data. As another example, when changes to stored data are substantially consolidated (e.g., changes are made to consecutive memory locations), it may be beneficial to update system data stored in the non-volatile memory more frequently. Reduction in write amplification, increase in efficiency, and reduction in start-up and initialization time can be attained. Reconstruction time of system data can also be reduced.

Abstract: Embodiments relate to implementing a coherence protocol. An aspect includes sending a request for data to a remote processor and receiving by a processor a response from the remote processor. The response has a transaction status of a remote transaction on the remote processor. The processor adds the transaction status of the remote transaction on the remote processor in a local transaction interference tracking table.

Abstract: A method is used in allocating blocks in storage systems. A block allocation request is received for a file of a file system. The block allocation request includes a data block allocation request and an indirect block allocation request. A type of the file is determined. A cylinder group is selected from a set of cylinder groups for allocating an indirect block based on the block allocation request. A set of data blocks is reserved for allocating a data block based on the type of the file.