Abstract: Managing data stored in a Data Storage Device (DSD) including a volatile memory and a non-volatile memory including a circular buffer. Metadata stored in the volatile memory is logically divided into blocks of metadata. At least one changed block of metadata is identified that has changed during operation of the DSD and the at least one changed block of metadata is stored in the circular buffer of the non-volatile memory.

Abstract: According to an aspect of an embodiment, a system of using an extensible language to represent storage metadata includes a computer-readable storage medium and a processing device. The computer-readable storage medium may have stored thereon storage metadata. The processing device may be configured to write the storage metadata to the computer-readable storage medium in an extensible language format. The processing device may also be configured to manipulate the storage metadata in the extensible language format. The processing device may also be configured to transfer the storage metadata in the extensible language format.

Abstract: A portion of a reprogrammable storage device is used to implement permanent data storage. The storage device includes a plurality of electrically erasable memory elements and a controller. The plurality of electrically erasable memory elements are configured to store data. Each memory element is programmable a number of write cycles before reaching a write failure state. The controller is coupled to the plurality of memory elements. The controller includes a receiver and a write engine. The receiver receives an instruction to drive a selected memory element to the write failure state. The write engine repeatedly writes a data value, in a plurality of write operations, to the selected memory element until the write failure state of the selected memory element is established.

Abstract: Embodiments relate to implementing a coherence protocol. An aspect includes sending a request for data to a remote processor and receiving by a processor a response from the remote processor. The response has a transaction status of a remote transaction on the remote processor. The processor adds the transaction status of the remote transaction on the remote processor in a local transaction interference tracking table.

Abstract: A writing method of a storage system which includes a host and a storage connected to the host, includes receiving journal data during a generation of a data writing transaction; inserting in a first map table, a plurality of entries, each entry including a first logical address of a first logical area of the storage and a second logical address of a second logical area of the storage; writing the journal data to a physical area of the storage corresponding to the first logical address; and remapping the physical area from the first logical address onto the second logical address using the plurality of entries when a size of a usable space of the first logical area is less than a desired value.

Abstract: A stack processor and method implemented using a ferroelectric random access memory (F-RAM) for code and a portion of the stack memory space having an instruction set optimized to minimize processor stack accesses and thus minimize program execution time. This is particularly advantageous in low power applications and those in which the power supply is only available for a finite period of time such as RFID implementations. Disclosed herein is a relatively small but complete set of instructions enabling a multitude of possible applications to be supported with a program execution time that is not too long.

Abstract: Storing defined presets for configuration of a storage controller may include providing a storage controller interface to define a preset associated with an action of the storage controller; receiving preset parameter values for the preset via the interface; validating the preset parameter values to check that the preset is valid; storing the preset within the storage controller, and creating one or more preset objects from the preset, the preset object being accessible by the storage controller at run time. The preset may include a human-readable name; an action name indicating to which associated storage controller action the preset applies, and a set of parameter name-value pairs.

Abstract: According to one embodiment, a semiconductor memory device includes a memory and a controller. The memory stores data pieces and search information including entries, where each entry is associated with a search key for specifying one data piece and a real address at which the data piece is stored. Upon reception of a first command, the controller, when the first command specifies a search key, outputs one data piece corresponding to one entry which includes the search key, and when the first command specifies one real address, outputs one data piece corresponding to one entry including the real address.

Abstract: Techniques for creating logical units associated with a data storage system. In one example, a method comprises the following steps. One or more blocks of source data associated with a data storage system are identified. The one or more blocks of source data are associated with at least a first logical unit that exists in the data storage system. A second logical unit is created which references the one or more identified blocks of source data.

Abstract: Methods and systems are disclosed for code protection in non-volatile memory (NVM) systems. Information stored within NVM memory sectors, such as boot code or other code blocks, is protected using lockout codes and lockout keys written in program-once memory areas within the NVM systems. Further, lockout codes can be combined into a merged lockout code that can be stored in a merged protection register. The merged protection register is used to control write access to protected memory sectors. Lockout code/key pairs are written to the program-once area when a memory sector is protected. The program-once area, which stores the lockout code/key pairs, is not readable by external users. Once protected, a memory sector can not be updated without the lockout code/key pair.

Abstract: Embodiments relate to controlling observability of transactional and non-transactional stores. An aspect includes receiving one or more store instructions. The one or more store instructions are initiated within an active transaction and include store data. The active transaction effectively delays committing stores to memory until successful completion of the active transaction. The store data is stored in a local storage buffer causing alterations to the local storage buffer from a first state to a second state. A signal is received that the active transaction has terminated. If the active transaction has terminated abnormally then: the local storage buffer is reverted back to the first state if the store data was stored by a transactional store instruction, and is propagated to a shared cache if the store instruction is non-transactional.

Abstract: To facilitate both minimal allocations and adaptive allocations, two sets of storage group policies are defined—one policy setting minimal allocation values for storage group access to storage resources and one policy setting maximal allocation values for storage group access to storage. In addition, a set of priority weights is specified that is used to balance access to storage tiers across storage groups. Upon existence of contention for storage resources, minimum allocation values for storage groups are determined based on the priority weights for the storage groups, resulting in threshold values being set to enable at least partial access to storage resources for all storage groups without requiring priority weighting of the activity density distributions of the competing storage groups. Allocations other than the minimal allocations are provided based on relative activity density distribution of storage extents between groups.

Abstract: Embodiments relate to controlling observability of transactional and non-transactional stores. An aspect includes receiving one or more store instructions. The one or more store instructions are initiated within an active transaction and include store data. The active transaction effectively delays committing stores to memory until successful completion of the active transaction. The store data is stored in a local storage buffer causing alterations to the local storage buffer from a first state to a second state. A signal is received that the active transaction has terminated. If the active transaction has terminated abnormally then: the local storage buffer is reverted back to the first state if the store data was stored by a transactional store instruction, and is propagated to a shared cache if the store instruction is non-transactional.

Abstract: An apparatus comprises a dynamic random-access memory (DRAM) for storing data. Refresh control circuitry is provided to control the DRAM to periodically perform a refresh cycle for refreshing the data stored in each memory location of the DRAM. A refresh address sequence generator generates a refresh address sequence of addresses identifying the order in which memory locations of the DRAM are refreshed during the refresh cycle. To deter differential power analysis attacks on secure data stored in the DRAM, the refresh address sequence is generated with the addresses of at least a portion of the memory locations in a random order which varies from refresh cycle to refresh cycle.

Abstract: Embodiments of the invention relate to hybrid address translation. An aspect of the invention includes receiving a first address, the first address referencing a location in a first address space. The computer searches a segment lookaside buffer (SLB) for a SLB entry corresponding to the first address; the SLB entry comprising a type field and an address field and determines whether a value of the type field in the SLB entry indicates a hashed page table (HPT) search or a radix tree search. Based on determining that the value of the type field indicates the HPT search, a HPT is searched to determine a second address, the second address comprising a translation of the first address into a second address space; and based on determining that the value of the type field indicates the radix tree search, a radix tree is searched to determine the second address.

Abstract: Embodiments of the invention relate to hybrid address translation. An aspect of the invention includes receiving a first address, the first address referencing a location in a first address space. The computer searches a segment lookaside buffer (SLB) for a SLB entry corresponding to the first address; the SLB entry comprising a type field and an address field and determines whether a value of the type field in the SLB entry indicates a hashed page table (HPT) search or a radix tree search. Based on determining that the value of the type field indicates the HPT search, a HPT is searched to determine a second address, the second address comprising a translation of the first address into a second address space; and based on determining that the value of the type field indicates the radix tree search, a radix tree is searched to determine the second address.

Abstract: A disk array device includes hard disks from which RAID groups are configured. Therein, a volume setting unit sets one or more used areas. A data check control unit determines, on the basis of the state into which the used areas have been set, which areas in the RAID groups are subject to a diagnosis. A data check execution unit that executes a cyclical diagnosis on the areas determined, by the data check control unit, to be those subject to a diagnosis.

Abstract: A memory system according to the embodiment comprises a memory device including a plurality of memory cells operative to store storage data, the storage containing input data from external to which parity information is added; and a memory controller operative to convert between the input data and the storage data, the storage data containing information data corresponding to the input data, and a relationship between the information data and the input data being nonlinearly.

Abstract: A memory system, comprises a nonvolatile memory comprising multiple memory cells, and a memory controller configured to control respective cell levels of the memory cells by assigning a logical address of each memory cell to one of multiple address groups according to a frequency with which the logical address has been accessed, determining a cell level for each address group, and controlling each memory cell to have the cell level of the address group to which its logical address is assigned.