Abstract: A novel air-gap-containing interconnect wiring structure is described incorporating a solid low-k dielectric in the via levels, and a composite solid plus air-gap dielectric in the wiring levels. Also provided is a method for forming such an interconnect structure. The method is readily scalable to interconnect structures containing multiple wiring levels, and is compatible with Dual Damascene Back End of the Line (BEOL) processing.

Abstract: A process wherein an insulating region is formed in a body at least around an array portion of a semiconductor body; a gate electrode of semiconductor material is formed on top of a circuitry portion of the semiconductor body; a first silicide protection mask is formed on top of the array portion; the gate electrode and the active areas of the circuitry portion are silicided and the first silicide protection mask is removed. The first silicide protection mask (is of polysilicon and is formed simultaneously with the gate electrode. A second silicide protection mask of dielectric material covering the first silicide protection mask is formed before silicidation of the gate electrode. The second silicide protection mask is formed simultaneously with spacers formed laterally to the gate electrode.

Abstract: The present invention relates generally to permanent interconnections between electronic devices, such as integrated circuit packages, chips, wafers and printed circuit boards or substrates, or similar electronic devices. More particularly it relates to high-density electronic devices. The invention describes means and methods that can be used to counteract the undesirable effects of thermal cycling, shock and vibrations and severe environment conditions in general. For leaded devices, the leads are oriented to face the thermal center of the devices and the system they interact with. For leadless devices, the mounting elements are treated or prepared to control the migration of solder along the length of the elements, to ensure that those elements retain their desired flexibility.

Abstract: An aluminum interconnect which extends adjacent to and is insulated from a stacked capacitor structure to facilitate electrical communication between an active device region of a semiconductor substrate of a semiconductor device structure and a bit line extending above the semiconductor substrate. The aluminum interconnect is disposed within a trench and may include a metal silicide layer adjacent the active device region to form a buried metal diffusion layer. The aluminum interconnect may also include a metal nitride layer disposed between the metal silicide and aluminum. The invention also includes methods of fabricating aluminum interconnects adjacent stacked capacitor structures and semiconductor device structures which include the aluminum interconnects.

Abstract: A semiconductor device has a semiconductor substrate of a first conductivity; and a first electrode formation region and a second electrode formation region formed adjacent to an inner surface of the semiconductor substrate. The first electrode formation regions and the second electrode formation regions are isolated from each other via an element isolation region. An upper first-type impurity layer and a lower first-type impurity layer are formed in one of the first electrode formation region and the second electrode formation region, the lower first-type impurity layer has a different first-type impurity concentration from the upper first-type impurity layer and is formed under the upper first-type impurity layer. A second-type impurity layer and a first-type impurity layer are formed in the other electrode formation region and the first-type impurity layer is formed under a part of the second-type impurity layer having second-type impurities.

Abstract: A method of manufacturing a semiconductor device including forming an insulator layer on an integrated circuit, forming a barrier layer having a first titanium film and a titanium nitride film on the insulator layer, heat-treating the barrier layer to release nitrogen gas from the titanium nitride film, forming a second titanium film on the barrier layer, and forming an aluminum film used as a wired metal on the second titanium film.

Abstract: A method of manufacturing a contact of a semiconductor device includes a series of pretreatment processes each performed in a plasma pretreatment module. A semiconductor substrate has an interlayer formed on an underlayer of a material containing silicon. A contact hole is formed in the interlayer to expose a surface of the underlayer. Subsequently, the semiconductor substrate is loaded into a plasma pretreatment module. The photoresist pattern is removed by ashing in the plasma pretreatment module. A damaged layer at the surface exposed by the contact hole is then removed in the plasma pretreatment module. Subsequently, the semiconductor substrate is pre-cleaned in the plasma pretreatment module. The semiconductor substrate is then transferred, while in a vacuum, to a deposition module. There, an upper layer is formed on the substrate to fill the contact hole.

Abstract: A method of manufacturing a semiconductor device comprises steps of: forming a first metal film having a reducing property on a semiconductor substrate; thermal treating the resulting semiconductor substrate for reducing a native oxide film naturally formed on the semiconductor substrate and for forming a first silicide film on the semiconductor substrate; removing an unreacted first metal film selectively; forming a second metal film on the semiconductor substrate; and thermal treating the resulting semiconductor substrate for forming a second silicide film on a surface of the semiconductor substrate which includes a region where the first silicide film is formed.

Abstract: In a method for manufacturing a memory cell of a nonvolatile semiconductor memory, a floating gate, first insulating film and control gate are successively stacked on a tunnel oxide film formed on a substrate of the nonvolatile semiconductor memory. The control gate, the first insulating film and the floating gate are patterned in stripes. Subsequently, a damaged portion of the tunnel oxide film immediately below a sidewall of the floating gate is removed by isotropic etching. A second insulating film is deposited to cover the control gate, sidewalls of the first insulating film, the floating gate and the tunnel oxide film. Thereby, a variation in threshold voltages between memory cells is suppressed.

Abstract: A method of forming a self-aligned contact pad for use in a semiconductor device, including: forming a gate having a gate mask formed thereon on a semiconductor substrate, the semiconductor substrate including an active region and a non-active region, forming a spacer on both sidewalls of the gate and the gate mask, forming an interlayer insulating layer over the entire surface of the semiconductor substrate, the interlayer insulating layer including an opening formed on the active region of the semiconductor substrate, forming a conductive material layer over the entire surface of the semiconductor substrate to cover the interlayer insulating layer, etching-back the conductive material layer until the interlayer insulating layer is exposed, and performing a multi-step CMP process to form contact pads in the opening of the interlayer insulating layer, such that the contact pads are electrically insulated from each other.

Abstract: A method of manufacturing semiconductor device which comprises the steps of forming an insulating film on an Si substrate provided with a wiring layer, forming a contact hole connected to the wiring layer and a wiring groove in the insulating film, filling the contact hole with an Si film, successively forming an Al film and a Ti film all over the substrate, performing a heat treatment thereby to substitute the Al film for the Ti film, and to allow the Si film to be absorbed by the Ti film, whereby filling the contact hole and wiring groove with the Al film, and removing a Ti/Ti silicide which is consisting of Ti silicide formed through the absorption of the Si film by the Ti film and a superfluous Ti, whereby filling the contact hole with an Al plug and filling the wiring groove with an Al wiring.

Abstract: The bipolar transistor is produced such that a connection region of its base is provided with a silicide layer, so that a base resistance of the bipolar transistor is small. No silicide layer is produced between an emitter and an emitter contact and between a connection region of a collector and a collector contact. The base is produced by in situ-doped epitaxy in a region in which a first insulating layer is removed by isotropic etching such that the connection region of the base which is arranged on the first insulating layer is undercut. In order to avoid defects of a substrate in which the bipolar transistor is partly produced, isotropic etching is used for the patterning of auxiliary layers, whereby etching is selective with respect to auxiliary layers lying above, which are patterned by anisotropic etching.