Abstract: An automatic delay adjusting method of a semiconductor integrated circuit includes placing a dummy wiring to a layout data and connecting the dummy wiring to a target wiring between a first cell and a second cell which is a timing violation occurs for the target wiring in the layout data. The dummy wiring connection includes replacing the dummy wiring with a dummy wiring cell having first and second pins corresponding to both ends of the dummy wiring, cutting the target wiring to generate first and second target wirings, connecting the first and second target wirings to the first and second pins, respectively, and replacing the dummy wiring cell with the dummy wiring to provide a wiring that is connected with the dummy wiring to the cut target wiring.

Abstract: Method, apparatus, and computer readable medium for implementing a circuit model in an integrated circuit are described. In some examples, the circuit model includes a communication channel between actors. Data portions of at least one data object passed between the actors over the communication channel are identified. An implementation is generated for the circuit model in which data portions are assigned to either local queue storage of the communication channel or centralized shared storage of the communication channel based on levels of access thereof by the actors.