Abstract: An embedded chip package (ECP) includes a plurality of re-distribution layers joined together in a vertical direction to form a lamination stack, each re-distribution layer having vias formed therein. The embedded chip package also includes a first chip embedded in the lamination stack and a second chip attached to the lamination stack and stacked in the vertical direction with respect to the first chip, each of the chips having a plurality of chip pads. The embedded chip package further includes an input/output (I/O) system positioned on an outer-most re-distribution layer of the lamination stack and a plurality of metal interconnects electrically coupled to the I/O system to electrically connect the first and second chips to the I/O system. Each of the plurality of metal interconnects extends through a respective via to form a direct metallic connection with a metal interconnect on a neighboring re-distribution layer or a chip pad on the first or second chip.

Abstract: The present invention provides a semiconductor-device copper-alloy bonding wire which has an inexpensive material cost, ensures a superior ball joining shape, wire joining characteristic, and the like, and a good loop formation characteristic, and a superior mass productivity. The semiconductor-device copper-alloy bonding wire contains at least one of Mg and P in total of 10 to 700 mass ppm, and oxygen within a range from 6 to 30 mass ppm.

Abstract: A deep trench is formed in a semiconductor-on-insulator (SOI) substrate and a pad layer thereupon. A conductive trench fill region is formed in the deep trench. A planarizing material layer having etch selectivity relative to the pad layer is applied. A portion of the pad layer having an edge that is vertically coincident with a sidewall of the deep trench is exposed by lithographic means. Exposed portion of the pad layer are removed selective to the planarizing material layer, followed by removal of exposed portion of a semiconductor layer selective to the conductive trench fill region by an anisotropic etch. The planarizing material layer is removed and a shallow trench isolation structure having a lower sidewall that is self-aligned to an edge of the original deep trench is formed. Another shallow trench isolation structure may be formed outside the deep trench concurrently.

Abstract: Example embodiments are directed to a polarized light emitting diode and method of forming the same. The polarized light emitting diode may include a support layer, a semiconductor layer structure, and/or a polarization control layer. The semiconductor layer structure may be formed on the support layer and may include a light-emitting layer. The polarization control layer may be formed on the semiconductor layer structure and may include a plurality of metal nanowires. The polarized light emitting diode may be configured to control the polarization of emitted light. The method of forming a polarized light emitting diode may include forming on a substrate a semiconductor layer structure with a light emitting layer. A reflecting layer may be formed on the semiconductor layer structure with an attached support layer. The substrate may be removed from the semiconductor layer structure and a polarization control layer including metal nanowires may be formed on the semiconductor layer structure.

Abstract: A method of forming a microelectronic package is provided. The method includes providing a silicon substrate having a plurality of carbon nanotubes disposed on a silicon layer and coupling the silicon substrate to a top surface of a packaging substrate, wherein the plurality of carbon nanotubes are coupled to a plurality of substrate pads of the packaging substrate. The method also includes removing the silicon substrate from the packaging substrate and disposing a die adjacent to the top surface of the packaging substrate, wherein the plurality of carbon nanotubes are coupled to a plurality of bump pads of the die.

Abstract: Methods and UBM structures having bilayer or trilayer UBM layers that include a thin TiW adhesion layer and a thick Ni-based barrier layer thereover both deposited under sputtering operating conditions that provide the resultant bilayer or trilayer UBM layers with minimal composite stresses. The Ni-based barrier layer may be pure Ni or a Ni alloy. These UBM layers may be patterned to fabricate bilayer or trilayer UBM capture pads, followed by joining a lead-free solder thereto for providing lead-free solder joints that maintain reliability after multiple reflows. Optionally, the top layer of the trilayer UBM structures may include soluble or insoluble metals for doping the lead-free solder connections.

Abstract: A process for fabricating an Integrated Circuit (IC) and the IC formed thereby is disclosed. The process comprises providing a substrate. The process further comprises forming a plurality of longitudinal trenches in the substrate and depositing a layer of a first conductive material on at least one longitudinal trench of the plurality of longitudinal trenches. A first layer of a second conductive material is deposited on the layer of the first conductive material. Thereafter, the process includes depositing a second layer of the second conductive material on the first layer of the second conductive material. The second layer of the second conductive material at least partially fills the at least one longitudinal trench. The first conductive material is selected such that a reduction potential of the first conductive material is less than a reduction potential of the second conductive material.

Abstract: Functionalized nanoparticles are deposited on metal lines inlaid in dielectric to form a metal cap layer that reduces electromigration in the metal line. The functionalized nanoparticles are deposited onto activated metal surfaces, then sintered and annealed to remove the functional agents leaving behind a continuous capping layer. The resulting cap layer is about 1 to 10 nm thick with 30-100% atomic of the nanoparticle material. Various semiconductor processing tools may be adapted for this deposition process without adding footprint in the semiconductor fabrication plant.

Abstract: A vertical structured Light Emitting Diode (LED) array using wafer level bonding. The process bonds two or more LED arrays vertically to produce light mixing in a small footprint. The vertically bonded LED array contains through substrate vias and a plurality of metal posts coated with solder to form an internal cavity between the LED layers. This LED array structure is intrinsically hermetically sealed.

Abstract: A stacked non-volatile memory device uses amorphous silicon based thin film transistors stacked vertically. Each layer of transistors or cells is formed from a deposited a-Si channel region layer having a predetermined concentration of carbon to form a carbon rich silicon film or silicon carbide film, depending on the carbon content. The dielectric stack is formed over the channel region layer. In one embodiment, the dielectric stack is an ONO structure. The control gate is formed over the dielectric stack. This structure is repeated vertically to form the stacked structure. In one embodiment, the carbon content of the channel region layer is reduced for each subsequently formed layer.

Abstract: A chip stack package may include a substrate, semiconductor chips, a molding member and a controller. The substrate may have a wiring pattern. The semiconductor chips may be stacked on a first surface of the substrate. Further, the semiconductor chips may be electrically connected to the wiring pattern. The molding member may be formed on the first substrate covering the semiconductor chips. The controller may be arranged on a second surface of the substrate. The controller may be electrically connected to the wiring pattern. The controller may have a selection function for selecting operable semiconductor chip(s) among the semiconductor chips.

Abstract: A semiconductor package includes a leadframe defining a die pad, a chip electrically coupled to the die pad, encapsulation material covering the chip and the die pad, and a plurality of lead ends exposed relative to the encapsulation material and configured for electrical communication with the chip, and a nitrogen-containing hydrocarbon coating disposed over at least the lead ends of the leadframe, where the hydrocarbon coating is free of metal particles.

Abstract: Disclosed are a light emitting device and a manufacturing method thereof. The light emitting device comprises a first conductive semiconductor layer, an active layer on the first conductive semiconductor, a second conductive semiconductor layer on the active layer, and a dot-shaped roughness layer on the second conductive semiconductor layer.

Abstract: An n-channel insulated gate semiconductor device with an active cell (5) comprising a p channel well region (6) surrounded by an n type third layer (8), the device further comprising additional well regions (11) formed adjacent to the channel well region (6) outside the active semiconductor cell (5) has enhanced safe operating are capability. The additional well regions (11) outside the active cell (5) do not affect the active cell design in terms of cell pitch, i.e. the design rules for cell spacing, and hole drainage between the cells, hence resulting in optimum carrier profile at the emitter side for low on-state losses.

Abstract: A fast injection optical switch is disclosed. The optical switch includes a thyristor having a plurality of layers including an outer doped layer and a switching layer. An area of the thyristor is configured to receive a light beam to be directed through at least one of the plurality of layers and exit the thyristor at a predetermined angle. At least two electrodes are coupled to the thyristor and configured to enable a voltage to be applied to facilitate carriers from the outer doped layer to be directed to the switching layer. Sufficient carriers can be directed to the switching layer to provide a change in refractive index of the switching layer to redirect at least a portion of the light beam to exit the thyristor at a deflection angle different from the predetermined angle.

Abstract: In accordance with the present invention, there is provided a semiconductor package (e.g., a QFP package) including a uniquely configured leadframe sized and configured to maximize the available number of exposed leads in the semiconductor package. More particularly, the semiconductor package of the present invention includes a generally planar die pad or die paddle defining multiple peripheral edge segments. In addition, the semiconductor package includes a plurality of leads. Some of these leads include exposed bottom surface portions which are provided in at least two concentric rows or rings which at least partially circumvent the die pad, with other leads including portions which protrude from respective side surfaces of a package body of the semiconductor package. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the leads.

Abstract: Provided is a light-emitting apparatus which can prevent a shadow mask from contacting a light-emitting medium to suppress damage of the medium, by using a conductive layer formed on a device isolation layer as a pressing member for the shadow mask, and can attain more secure conduction between a second electrode and an auxiliary electrode.

Abstract: A semiconductor package and method of fabricating has a substrate having conductive patterns formed thereon. A semiconductor die is attached to the substrate. An electrically connecting member is electrically coupled to the semiconductor die and the conductive patterns. A plurality of lands is coupled to the substrate. At least one land is pivotally mounted to the substrate. A first section of the pivotally mounted land is in contact with the substrate. A second section of the pivotally mounted land is floating to form a void area between the substrate and the second section. An encapsulant is used for encapsulating a top surface of the substrate, the semiconductor die, and the electrically connecting member. A solder ball is electrically coupled to each land.

Abstract: A gas or an insulating material having a relative dielectric constant of not more than 2.5 on average is interposed between a first wiring layer and a second wiring layer included in a multilayer wiring structure. Between a wiring of the first wiring layer and a wiring of the second wiring layer, a conductive connector is arranged. Between a predetermined wiring of the first wiring layer and a predetermined wiring of the second wiring layer, an insulating heat conductor having a relative dielectric constant of not more than 5 is arranged.

Abstract: A chip structure comprising a silicon substrate, a MOS device, dielectric layers, a metallization structure, a passivation layer, a plurality of metal layers and a polymer layer. The metallization structure comprises a first circuit layer and a second circuit layer over the first circuit layer, and comprises a damascene electroplated copper. The passivation layer is over the metallization structure and dielectric layers, the passivation layer including a first opening exposing a contact point of the metallization structure. The polymer layer is disposed over the passivation layer and the first metal layer, a second opening in the polymer layer being over a second contact point of the first metal layer, the polymer layer covering a top surface and sidewall of the first metal layer. The second contact point is connected to the first contact point through the first opening, the second opening not being vertically over the first opening.